PIC18F87J60-I/PT Microchip Technology, PIC18F87J60-I/PT Datasheet - Page 14
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PIC18F87J60-I/PT
Manufacturer Part Number
PIC18F87J60-I/PT
Description
IC PIC MCU FLASH 64KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F63J11-IPT.pdf
(36 pages)
3.PIC18F66J65-IPT.pdf
(8 pages)
4.PIC18F66J65-IPT.pdf
(480 pages)
5.PIC18F66J65-IPT.pdf
(4 pages)
6.PIC18F66J65-IPT.pdf
(10 pages)
7.PIC18F97J60-IPT.pdf
(476 pages)
Specifications of PIC18F87J60-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
80-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
55
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 15x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
55
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
15-ch x 10-bit
Package
80TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
41.667 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F87J60-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F87J60-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC18F6XJXX/8XJXX
3.0
Programming includes the ability to erase or write the
memory within the device.
The EECON1 register is used to control Write or Row
Erase operations. The WREN bit (EECON1<2>) must
be set to enable writes; this must be done prior to
initiating a write sequence. It is strongly recommended
that the WREN bit only be set immediately prior to a
program or erase operation.
3.1
3.1.1
The PIC18F6XJXX/8XJXX devices may be Bulk
Erased by writing 0180h to the table address,
3C0005h:3C0004h. The basic sequence is shown in
Table 3-1 and demonstrated in Figure 3-1.
Since the code-protect Configuration bit is stored in the
program code within code memory, a Bulk Erase
operation will also clear any code-protect settings for
the device.
The actual Bulk Erase function is a self-timed
operation. Once the erase has started (falling edge of
the 4th PGC after the NOP command), serial execution
will cease until the erase completes (parameter, P11).
During this time, PGC may continue to toggle but PGD
must be held low.
FIGURE 3-2:
DS39644L-page 14
Note:
Note:
PGC
PGD
4-Bit Command
DEVICE PROGRAMMING
ICSP Erase
1
0
The EECON1 register is available only in
ICSP Programming mode. In normal
operating modes, the corresponding SFR
location (FA6h) is unimplemented. Writes
to the register during code execution will
have no effect; reading the location will
return ‘0’s.
ICSP BULK ERASE
A Bulk Erase is the only way to reprogram
the code-protect Configuration bit from an
ON state to an OFF state.
2
0
3
1
4
1
P5
BULK ERASE TIMING
1
1
Data Payload
2
1
16-Bit
15 16
0
0
P5A
4-Bit Command
1
0
2
0
3
0
PGD = Input
4
0
P5
1
0
Data Payload
2
0
16-Bit
TABLE 3-1:
FIGURE 3-1:
Command
15 16
0
0000
0000
0000
0000
0000
0000
1100
0000
0000
0000
0000
0000
0000
1100
0000
0000
4-Bit
0
P5A
4-Bit Command
1
0
Payload
2
0E 3C
6E F8
0E 00
6E F7
0E 05
6E F6
01 01
0E 3C
6E F8
0E 00
6E F7
0E 04
6E F6
80 80
00 00
00 00
0
Data
3
BULK ERASE COMMAND
SEQUENCE
0 0
3C0004h to Erase
Write 8080h to
4
Entire Device
Write 0101h
to 3C0005h
BULK ERASE FLOW
Delay P11
2009 Microchip Technology Inc.
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 05h
MOVWF TBLPTRL
Write 01h to 3C0005h
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 04h
MOVWF TBLPTRL
Write 80h TO 3C0004h to
erase entire device.
NOP
Hold PGD low until erase
completes.
Done
Time
Start
Erase Time
P11
Core Instruction
P5
Data Payload
16-Bit
1
n
2
n