PIC18F87J60-I/PT Microchip Technology, PIC18F87J60-I/PT Datasheet - Page 18

• Manufacturer Part Number: PIC18F87J60-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J60-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 55
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 15-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6XJXX/8XJXX
3.2.1
The previous programming example assumed that the
device had been Bulk Erased prior to programming. It
may be the case, however, that the user wishes to
modify only a section of an already programmed
device.
The appropriate number of bytes required for the erase
buffer (1,024 bytes) must be read out of code memory
(as described in Section 4.2 “Verify Code Memory
and Configuration Word”) and buffered. Modifica-
tions can be made on this buffer. Then, the row of code
memory that was read out must be erased and rewrit-
ten with the modified data. The code sequence is
shown in Table 3-4. The WREN bit must be set if the
WR bit in EECON1 is used to initiate a write sequence.
TABLE 3-4:
DS39644L-page 18
Step 1: Direct access to code memory.
Step 2: Read and modify code memory.
Step 3: Enable memory writes and set up an erase.
Step 4: Load write buffer. The correct bytes will be selected based on the Table Pointer.
To continue modifying data, repeat Step 5, where the Address Pointer is incremented by 1024 bytes at each iteration of the loop.
Step 5: Disable writes.
Command
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1101
1111
0000
0000
4-Bit
.
.
.
MODIFYING CODE MEMORY
0E <Addr[21:16]>
6E F8
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
82 A6
88 A6
82 A6
00 00
0E <Addr[21:16]>
6E F8
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
<MSB><LSB>
<MSB><LSB>
00 00
94 A6
MODIFYING CODE MEMORY
Data Payload
.
.
.
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BSF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
Write 2 bytes and post-increment address by 2.
Repeat as many times as necessary to fill the write buffer.
Write 2 bytes and start programming.
NOP - hold PGC high for time P9.
BCF
EECON1, WREN
EECON1, FREE
EECON1, WR
NOP – hold PGC high for time P10.
<Addr[21:16]>
TBLPTRU
<Addr[8:15]>
TBLPTRH
<Addr[7:0]>
TBLPTRL
<Addr[21:16]>
TBLPTRU
<Addr[8:15]>
TBLPTRH
<Addr[7:0]>
TBLPTRL
EECON1, WREN
3.2.2
Since the Flash Configuration Words are stored in
program memory, they are programmed as if they were
program data. Refer to Section 3.2 “Code Memory
Programming” and Section 3.2.1 “Modifying Code
Memory” for methods and examples on programming
or modifying program memory. See also Section 5.0
“Configuration Word” for additional information on
the Configuration Words.
Core Instruction
CONFIGURATION WORD
PROGRAMMING
 2009 Microchip Technology Inc.