AT89C5130A-PUTUM Atmel, AT89C5130A-PUTUM Datasheet - Page 110

• Manufacturer Part Number: AT89C5130A-PUTUM
• Description: IC 8051 MCU FLASH 16K USB 32QFN
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5130A-PUTUM

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Package: 32QFN EP
• Device Core: 8051
• Family Name: 89C
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: SPI/TWI/UART/USB
• Number Of Timers: 3
• Processor Series: AT89x
• Core: 8051
• Data Ram Size: 1.25 KB
• Maximum Clock Frequency: 48 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89STK-05
• Minimum Operating Temperature: - 40 C
• Height: 0.95 mm
• Length: 7 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C5130A-PUTIM; AT89C5130A-PUTIM

Table 20-5.
110
SSSTA
Status
Code
08h
10h
18h
20h
28h
30h
38h
Status of the Two-
wire Bus and Two-
wire Hardware
A START condition has
been transmitted
A repeated START
condition has been
transmitted
SLA+W has been
transmitted; ACK has
been received
SLA+W has been
transmitted; NOT ACK
has been received
Data byte has been
transmitted; ACK has
been received
Data byte has been
transmitted; NOT ACK
has been received
Arbitration lost in
SLA+W or data bytes
AT89C5130A/31A-M
Status in Master Transmitter Mode
To/From SSDAT
Write SLA+W
Write SLA+W
Write SLA+R
Write data byte
No SSDAT action
No SSDAT action
No SSDAT action
Write data byte
No SSDAT action
No SSDAT action
No SSDAT action
Write data byte
No SSDAT action
No SSDAT action
No SSDAT action
Write data byte
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
Application software response
SSSTA
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SSSTO
To SSCON
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
SSI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSAA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Next Action Taken by Two-wire Hardware
SLA+W will be transmitted.
SLA+W will be transmitted.
SLA+R will be transmitted.
Logic will switch to master receiver mode
Data byte will be transmitted.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Data byte will be transmitted.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Data byte will be transmitted.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Data byte will be transmitted.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Two-wire bus will be released and not addressed
slave mode will be entered.
A START condition will be transmitted when the bus
becomes free.
4337K–USB–04/08