AT89C5130A-PUTUM Atmel, AT89C5130A-PUTUM Datasheet - Page 71

• Manufacturer Part Number: AT89C5130A-PUTUM
• Description: IC 8051 MCU FLASH 16K USB 32QFN
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5130A-PUTUM

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Package: 32QFN EP
• Device Core: 8051
• Family Name: 89C
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: SPI/TWI/UART/USB
• Number Of Timers: 3
• Processor Series: AT89x
• Core: 8051
• Data Ram Size: 1.25 KB
• Maximum Clock Frequency: 48 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89STK-05
• Minimum Operating Temperature: - 40 C
• Height: 0.95 mm
• Length: 7 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C5130A-PUTIM; AT89C5130A-PUTIM

15.2.2
15.2.3
4337K–USB–04/08
Broadcast Address
Reset Addresses
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t care bit; for slaves B and C, bit 0 is a 1. To communicate
with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves
B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111
0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1
clear, and bit 2 clear (e.g. 1111 0001b).
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with
zeros defined as don’t care bits, e.g.:
The use of don’t care bits provides flexibility in defining the broadcast address, in most applica-
tions, a broadcast address is FFh. The following is an example of using broadcast addresses:
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of
the slaves, the master must send an address FFh. To communicate with slaves A and B, but not
slave C, the master can send and address FBh.
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast
addresses are XXXX XXXXb (all don’t care bits). This ensures that the serial port will reply to any
address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not
support automatic address recognition.
Slave C:SADDR1111 0011b
Slave A:SADDR1111 0001b
Slave B:SADDR1111 0011b
Slave C:SADDR = 1111 0011b
Broadcast = SADDR OR SADEN1111 111Xb
SADEN1111 1101b
Given1111 00X1b
SADDR0101 0110b
SADEN1111 1100b
SADEN1111 1010b
Broadcast1111 1X11b,
SADEN1111 1001b
Broadcast1111 1X11B,
SADEN1111 1101b
Broadcast1111 1111b
AT89C5130A/31A-M
71