PIC18F2550-I/SP Microchip Technology, PIC18F2550-I/SP Datasheet - Page 203

• Manufacturer Part Number: PIC18F2550-I/SP
• Description: IC PIC MCU FLASH 16KX16 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2550-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: SPI, I2C, EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163025, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRDDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.3.8
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
In most idle modes, a clock is provided to the peripher-
als. That clock should be from the primary clock
source, the secondary clock (Timer1 oscillator) or the
INTOSC source. See Section 2.4 “Clock Sources
and Oscillator Switching” for additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP interrupts are enabled, they can wake the con-
troller from Sleep mode or one of the Idle modes when
the master completes sending data. If an exit from
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the devices wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI Transmit/
Receive Shift register. When all eight bits have been
received, the MSSP interrupt flag bit will be set and if
enabled, will wake the device.
TABLE 19-2:
© 2006 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
TRISA
TRISB
TRISC
SSPBUF
SSPCON1
SSPSTAT
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
Note 1:
Name
2:
These bits are unimplemented in 28-pin devices; always maintain these bits clear.
RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled,
all of the associated bits read ‘0’.
OPERATION IN POWER-MANAGED
MODES
Synchronous Serial Port Receive Buffer/Transmit Register
GIE/GIEH PEIE/GIEL TMR0IE
SPPIF
SPPIE
SPPIP
TRISC7
TRISB7
WCOL
Bit 7
SMP
—
REGISTERS ASSOCIATED WITH SPI OPERATION
(1)
(1)
(1)
TRISA6
TRISB6
TRISC6
SSPOV
ADIE
ADIP
ADIF
Bit 6
CKE
(2)
TRISA5
TRISB5
SSPEN
RCIF
RCIE
RCIP
Bit 5
D/A
—
PIC18F2455/2550/4455/4550
TRISA4
TRISB4
Preliminary
INT0IE
TXIF
TXIE
TXIP
Bit 4
CKP
—
P
TRISA3
TRISB3
SSPM3
SSPIE
SSPIP
SSPIF
19.3.9
A Reset disables the MSSP module and terminates the
current transfer.
19.3.10
Table 19-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 19-1:
There is also an SMP bit which controls when the data
is sampled.
RBIE
Bit 3
—
Standard SPI Mode
S
Terminology
0, 0
0, 1
1, 0
1, 1
TMR0IF
CCP1IF
CCP1IE
CCP1IP
TRISC2
TRISA2
TRISB2
SSPM2
EFFECTS OF A RESET
BUS MODE COMPATIBILITY
Bit 2
R/W
SPI BUS MODES
TMR2IE
TMR2IP
TMR2IF
TRISA1
TRISB1
TRISC1
SSPM1
INT0IF
Bit 1
UA
CKP
Control Bits State
0
0
1
1
TMR1IF
TMR1IE
TMR1IP
TRISA0
TRISB0
TRISC0
SSPM0
RBIF
Bit 0
DS39632C-page 201
BF
CKE
on page
Values
Reset
1
0
1
0
51
54
54
54
54
54
54
52
52
52