PIC18LF4331-I/P Microchip Technology, PIC18LF4331-I/P Datasheet - Page 168
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PIC18LF4331-I/P
Manufacturer Part Number
PIC18LF4331-I/P
Description
IC PIC MCU FLASH 4KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(4 pages)
8.PIC18LF2331-ISO.pdf
(40 pages)
9.PIC18F4331-EP.pdf
(400 pages)
Specifications of PIC18LF4331-I/P
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF4331-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
PIC18LF4331-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC18F2331-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18LF2331-ISO PDF datasheet #7
- PIC18LF2331-ISO PDF datasheet #8
- PIC18F4331-EP PDF datasheet #9
- Current page: 168 of 392
- Download datasheet (4Mb)
PIC18F2331/2431/4331/4431
FIGURE 17-13:
17.2.6.2
The velocity event pulse (velcap, see
serves as the TMR5 capture trigger to IC1 while in the
Velocity mode. The number of velocity events are
reduced by the velocity postscaler before they are used
as the input capture clock. The velocity event reduction
ratio can be set with the PDEC<1:0> control bits
(QEICON<1:0>) to 1:4, 1:16, 1:64 or no reduction (1:1).
The velocity postscaler settings are automatically
reloaded from their previous values as the Velocity
mode is re-enabled.
DS39616D-page 168
Note 1: Timing shown is for QEIM<2:0> = 101, 110 or 111 (x4 Update mode enabled) and the velocity postscaler divide ratio
QEA
QEB
vel_out
velcap
TMR5
VELR
cnt_reset
IC1IF
CAP1REN
Instr.
Execution
2: The VELR register latches the TMR5 count on the “velcap” capture pulse. Timer5 must be set to the Synchronous Timer
3: The TMR5 counter is reset on the next Q1 clock cycle following the “velcap” pulse. The TMR5 value is unaffected
4: IC1IF interrupt is enabled by setting IC1IE as follows: BSF PIE2, IC1IE. Assume IC1E bit is placed in the PIE2
5: The post decimation value is changed from PDEC = 01 (decimate by 4) to PDEC = 00 (decimate by 1).
is set to divide-by-4 (PDEC<1:0> = 01).
or Counter mode. In this example, it is set to the Synchronous Timer mode, where the TMR5 prescaler divide ratio = 1
(i.e., Timer5 Clock = T
when the Velocity Measurement mode is first enabled (VELM = 0). The velocity postscaler values must be
reconfigured to their previous settings when re-entering Velocity Measurement mode. While making speed
measurements of very slow rotational speeds (e.g., servo-controller applications), the Velocity Measurement mode
may not provide sufficient precision. The Pulse-Width Measurement mode may have to be used to provide the
additional precision. In this case, the input pulse is measured on the CAP1 input pin.
(Peripheral Interrupt Enable 2) register in the target device. The actual IC1IF bit is written on the Q2 rising edge.
(4)
(2)
(2)
Velocity Postscaler
(3)
BCF T5CON, VELM
VELOCITY MEASUREMENT TIMING
Old Value
CY
BCF PIE2, IC1IE
).
Figure
Q1
17-12)
BSF PIE2, IC1IE
Forward
1529
Q1
17.2.6.3
The TMR5 value can be reset (TMR5 register
pair = 0000h) on a velocity event capture by setting
the CAP1REN bit (CAP1CON<6>). When CAP1REN
is cleared, the TMR5 time base will not be reset on
any velocity event capture pulse. The VELR register
pair, however, will continue to be updated with the
current TMR5 value.
(1)
MOVWF QEICON
1537
Reverse
CAP1REN in Velocity Mode
(5)
Q1
2010 Microchip Technology Inc.
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