ATMEGA16L-8AU Atmel, ATMEGA16L-8AU Datasheet - Page 234
ATMEGA16L-8AU
Manufacturer Part Number
ATMEGA16L-8AU
Description
IC AVR MCU 16K 8MHZ 3V 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA16L-8AU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
JTAG/SPI/UART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Scanning the RESET
Pin
Scanning the Clock
Pins
2466T–AVR–07/10
Figure 118. Additional Scan Signal for the Two-wire Interface
The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high
logic for High Voltage Parallel Programming. An observe-only cell as shown in
inserted both for the 5V reset signal; RSTT, and the 12V reset signal; RSTHV.
Figure 119. Observe-only Cell
The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscilla-
tor, External RC, External Clock, (High Frequency) Crystal Oscillator, Low Frequency Crystal
Oscillator, and Ceramic Resonator.
Figure 120
The Enable signal is supported with a general boundary-scan cell, while the Oscillator/Clock out-
put is attached to an observe-only cell. In addition to the main clock, the Timer Oscillator is
scanned in the same way. The output from the internal RC Oscillator is not scanned, as this
Oscillator does not have external connections.
From System Pin
shows how each Oscillator with external connection is supported in the scan chain.
Pxn
Previous
From
Cell
ShiftDR
0
1
ClockDR
D
Slew-rate Limited
FF1
Q
Next
SRC
Cell
To
ATmega16(L)
To System Logic
ODxn
TWIEN
IDxn
OCxn
PUExn
Figure 119
234
is
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