T89C51RD2-SMSIM Atmel, T89C51RD2-SMSIM Datasheet - Page 38
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T89C51RD2-SMSIM
Manufacturer Part Number
T89C51RD2-SMSIM
Description
IC MICRO CTRL 64K FLASH 68PLCC
Manufacturer
Atmel
Series
89Cr
Datasheet
1.T89C51RD2-SMSIM.pdf
(104 pages)
Specifications of T89C51RD2-SMSIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
48
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Interrupt System
Figure 16. Interrupt Control System
38
EXF2
INT0
INT1
PCA IT
TF0
TF1
TF2
T89C51RD2
RI
TI
Individual Enable
IE0
IE1
The T89C51RD2 has a total of 7 interrupt vectors: two external interrupts (INT0 and
INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt and the PCA glo-
bal interrupt. These interrupts are shown in Figure 16.
Each of the interrupt sources can be individually enabled or disabled by setting or clear-
ing a bit in the Interrupt Enable register (See Table 23.). This register also contains a
global disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority lev-
els by setting or clearing a bit in the Interrupt Priority register (See Table 24.) and in the
Interrupt Priority High register (See Table 22). shows the bit values and priority levels
associated with each combination.
Table 22. Priority Level Bit Values
IPH.x
0
0
1
1
IPH, IP
IP.x
0
1
0
1
3
0
3
0
3
0
3
0
3
0
3
0
3
0
Global Disable
Interrupt Level Priority
3 (Highest)
0 (Lowest)
High priority
interrupt
1
2
Interrupt
polling
sequence, decreasing from
high to low priority
Low priority
interrupt
4243G–8051–05/03