ATMEGA16L-8PU Atmel, ATMEGA16L-8PU Datasheet - Page 176
![IC AVR MCU 16K 8MHZ 3V 40DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA16L-8PU
Manufacturer Part Number
ATMEGA16L-8PU
Description
IC AVR MCU 16K 8MHZ 3V 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA16L-8MI.pdf
(26 pages)
2.ATMEGA16L-8MI.pdf
(357 pages)
3.ATMEGA16-16PU.pdf
(358 pages)
Specifications of ATMEGA16L-8PU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
JTAG/SPI/UART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
A/d Inputs
8-Channel, 10-Bit
Cpu Speed
8 MIPS
Eeprom Memory
512 Bytes
Input Output
32
Interface
JTAG/SPI/UART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
16K Bytes
Timers
2-8-bit, 1-16-bit
Voltage, Range
2.7-5.5 V
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 176 of 357
- Download datasheet (8Mb)
Multi-master Bus
Systems,
Arbitration and
Synchronization
2466T–AVR–07/10
The TWI protocol allows bus systems with several Masters. Special concerns have been taken
in order to ensure that transmissions will proceed as normal, even if two or more Masters initiate
a transmission at the same time. Two problems arise in multi-master systems:
•
•
The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from
all Masters will be wired-ANDed, yielding a combined clock with a high period equal to the one
from the Master with the shortest high period. The low period of the combined clock is equal to
the low period of the Master with the longest low period. Note that all Masters listen to the SCL
line, effectively starting to count their SCL high and low time-out periods when the combined
SCL line goes high or low, respectively.
Figure 82. SCL Synchronization between Multiple Masters
Arbitration is carried out by all Masters continuously monitoring the SDA line after outputting
data. If the value read from the SDA line does not match the value the Master had output, it has
lost the arbitration. Note that a Master can only lose arbitration when it outputs a high SDA value
while another Master outputs a low value. The losing Master should immediately go to Slave
mode, checking if it is being addressed by the winning Master. The SDA line should be left high,
but losing Masters are allowed to generate a clock signal until the end of the current data or
address packet. Arbitration will continue until only one Master remains, and this may take many
bits. If several Masters are trying to address the same Slave, arbitration will continue into the
data packet.
An algorithm must be implemented allowing only one of the Masters to complete the
transmission. All other Masters should cease transmission when they discover that they
have lost the selection process. This selection process is called arbitration. When a
contending Master discovers that it has lost the arbitration process, it should immediately
switch to Slave mode to check whether it is being addressed by the winning Master. The fact
that multiple Masters have started transmission at the same time should not be detectable to
the Slaves, that is, the data being transferred on the bus must not be corrupted.
Different Masters may use different SCL frequencies. A scheme must be devised to
synchronize the serial clocks from all Masters, in order to let the transmission proceed in a
lockstep fashion. This will facilitate the arbitration process.
SCL from
SCL from
Master A
Master B
SCL bus
Line
TA
Counting Low Period
low
Masters Start
TB
low
TA
Counting High Period
high
Masters Start
TB
high
ATmega16(L)
176
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