DSPIC30F4013-30I/P Microchip Technology, DSPIC30F4013-30I/P Datasheet - Page 9

• Manufacturer Part Number: DSPIC30F4013-30I/P
• Description: IC DSPIC MCU/DSP 48K 40DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-30I/P

• Program Memory Type: FLASH
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Data Rom Size: 1024 B
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F003 - MODULE SOCKET DSPIC30F 40DIPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F4013-30IP

35.3.2.1
© 2008 Microchip Technology Inc.
Master Mode
Section 35. Serial Peripheral Interface (SPI) (Part II)
In Master mode, the system clock is prescaled and then used as the serial clock. The prescaling
is based on the settings in the PPRE<1:0> (SPI1CON1<1:0>) and SPRE<2:0>
(SPI1CON1<4:2>) bits. The serial clock is output via the SCK1 pin to the slave devices. The
clock pulses are only generated when there is data to be transmitted. For further information,
refer to 35.4 “Master Mode Clock Frequency”. The CKP and CKE bits determine on which
edge of the clock data transmission occurs.
Both data to be transmitted and data received are, respectively, written into or read from the
SPI1BUF register.
The following describes the SPI1 module operation in Master mode:
1.
2.
3.
4.
5.
Note:
Once the module is set up for the Master mode of operation and enabled, data to be
transmitted is written to the SPI1BUF register. The SPITBF (SPI1STAT<1>) bit is set.
The contents of SPI1TXB are moved to the shift register, SPI1SR, and the SPITBF bit is
cleared by the module.
A series of 8/16 clock pulses shifts out 8/16 bits of transmit data from the SPI1SR to the
SDO1 pin and simultaneously shifts in the data at the SDI1 pin into the SPI1SR.
When the transfer is complete, the following events occur:
a)
b)
c)
d)
If the SPIRBF bit is set (receive buffer is full) when the SPI1 module needs to transfer data
from SPI1SR to SPI1RXB, the module will set the SPIROV (SPI1STAT<6>) bit, indicating
an overflow condition.
Data to be transmitted can be written to SPI1BUF by the user application at any time as
long as the SPITBF (SPI1STAT<1>) bit is clear. The write can occur while SPI1SR is
shifting out the previously written data, allowing continuous transmission.
The interrupt flag bit, SPI1IF, is set. SPI1 interrupts can be enabled by setting the
interrupt enable bit, SPI1IE. The SPI1IF flag is not cleared automatically by the
hardware.
When the ongoing transmit and receive operation is completed, the contents of the
SPI1SR register are moved to the SPI1RXB register.
The SPIRBF (SPI1STAT<0>) bit is set by the module, indicating that the receive buf-
fer is full.
Once the SPI1BUF register is read by the user application, the hardware clears the
SPIRBF bit.
The SPI1SR register cannot be written into directly by the user application. All writes
to the SPI1SR register are performed through the SPI1BUF register.
DS70272B-page 35-9
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