PIC16F84-10I/P Microchip Technology, PIC16F84-10I/P Datasheet - Page 451

• Manufacturer Part Number: PIC16F84-10I/P
• Description: IC MCU FLASH 1KX14 EE 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F84-10I/P

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 68 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16F
• No. Of I/o's: 13
• Eeprom Memory Size: 64Byte
• Ram Memory Size: 68Byte
• Cpu Speed: 10MHz
• No. Of Timers: 1
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 68 B
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 1
• Operating Supply Voltage: 2 V to 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

24.3.2
24.3.3
24.3.4
24.3.5
24.3.6
1997 Microchip Technology Inc.
Sleep Operation
Effects of a Reset
Slope A/D Comparator
Analog MUX
Programmable Current Source
The Slope A/D may operate when the device is in Sleep mode. For the Slope A/D to do a con-
version during Sleep mode, the Slope A/D module must have a device clock. For a clock to be
present the OSCOFF bit must be cleared before going to SLEEP. Also the REFOFF and ADOFF
bits must be cleared to ensure that the results reflect the voltage on the input channel. By doing
an A/D conversion during Sleep mode, the result has improved accuracy due to a reduction of
system noise.
When the device clock is disabled, the Slope A/D Timer (ADTMRH:ADTMRL) stops increment-
ing. Even if the Slope A/D module is not disabled, the slope A/D cannot wake-up the device. This
is because the ADCIF bit cannot be set, which is one of the control bits used to wake the device
from SLEEP mode. When the device awakes, if the comparator value has tripped, the capture
and interrupt will occur. The value in the ADCAP registers is meaningless.
For maximum power savings, all analog components of the Slope A/D module should be disabled
(no conversion in progress).
After any device reset, the Slope A/D module is disabled (lowest current state) and the device
I/O are configured as analog channels.
This module includes a high gain comparator for Slope A/D conversions. The non-inverting
input terminal of the Slope A/D comparator is connected to the output of an analog MUX through
an RC low-pass filter. The inverting input terminal is connected to the external ramp capacitor.
The output of the comparator is used to cause the capture event to occur. This causes the value
in the ADTMR registers to be loaded into the ADCAP registers. This output will also cause the
ADCIF bit to be set.
A total of 16 channels are internally multiplexed to the single Slope A/D comparator positive input.
Four configuration bits (ADCON0<7:4>) select the channel to be converted.
Four configuration bits (ADCON1<7:4>) are used to control a programmable current source for
generating the ramp voltage to the Slope A/D comparator. This allows compensation for full-scale
input voltage, clock frequency and the external capacitor tolerance variations.
Setting the ADRST bit disconnects the current source from the CDAC pin. Current flow begins
when the ADRST bit is cleared.
The programmable current source output is tied to the CDAC pin. This current source is used to
charge an external capacitor, which generates the ramp voltage for the Slope A/D comparator
(Figure
24-1).
Section 24. Slope A/D
DS31024A-page 24-9
24