AT89C5130A-RDTUM Atmel, AT89C5130A-RDTUM Datasheet - Page 69
![IC 8051 MCU FLASH 16K USB 64VQFP](/photos/6/81/68127/313-64-vqfp_sml.jpg)
AT89C5130A-RDTUM
Manufacturer Part Number
AT89C5130A-RDTUM
Description
IC 8051 MCU FLASH 16K USB 64VQFP
Manufacturer
Atmel
Series
AT89C513xr
Datasheet
1.AT89C5130A-PUTUM.pdf
(188 pages)
Specifications of AT89C5130A-RDTUM
Core Processor
C52X2
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
LED, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
2-Wire, EUART, SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
34
Number Of Timers
16 bit
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89STK-05
Minimum Operating Temperature
- 40 C
Package
64VQFP
Device Core
8051
Family Name
89C
Maximum Speed
48 MHz
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
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15. Serial I/O Port
15.1
4337K–USB–04/08
Framing Error Detection
The serial I/O port in the AT89C5130A/31A-M is compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as an Uni-
versal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (modes 1, 2
and 3). Asynchronous transmission and reception can occur simultaneously and at different
baud rates.
Serial I/O port includes the following enhancements:
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To
enable the framing bit error detection feature, set SMOD0 bit in PCON register (see Figure 15-
1).
Figure 15-1. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.
An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by
two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See
15-1) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set, only soft-
ware or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear
FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See
15-2
Figure 15-2. UART Timings in Mode 1
• Framing error detection
• Automatic address recognition
and
Figure
SMOD0 = X
SMOD0 = 1
RXD
15-3).
SM0/FE
FE
RI
SMOD1
SMOD0
SM1
Start
Bit
D0
SM2
-
D1
REN
Set FE Bit if Stop Bit is 0 (framing error) (SMOD0 = 1)
SM0 to UART Mode Control (SMOD0 = 0)
POF
To UART Framing Error Control
D2
TB8
GF1
D3
Data Byte
RB8
GF0
D4
AT89C5130A/31A-M
D5
PD
TI
D6
IDL
RI
D7
SCON (98h)
PCON (87h)
Stop
Bit
Figure
Table
69
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