ATMEGA169P-16AU Atmel, ATMEGA169P-16AU Datasheet - Page 23
![IC AVR MCU 16K 16MHZ IND 64-TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA169P-16AU
Manufacturer Part Number
ATMEGA169P-16AU
Description
IC AVR MCU 16K 16MHZ IND 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA169P-16AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI/USART/USI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
54
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRBFLY
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
64TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA169P-16AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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7.3
7.3.1
8018P–AVR–08/10
EEPROM Data Memory
EEPROM Read/Write Access
The ATmega169P contains 512 bytes of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles. This section describes the access between the EEPROM and
the CPU, specifying the EEPROM Address Registers, the EEPROM Data Register, and the
EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see
”Serial Downloading” on page
”Parallel Programming Parameters, Pin Mapping, and Commands” on page 299
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
however, lets the user software detect when the next byte can be written. If the user code con-
tains instructions that write the EEPROM, some precautions must be taken. In heavily filtered
power supplies, V
some period of time to run at a voltage lower than specified as minimum for the clock frequency
used. See
these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
The following procedure should be followed when writing the EEPROM (the order of steps 3 and
4 is not essential). See
tion for each register bit:
1. Wait until EEWE becomes zero.
2. Wait until SPMEN in SPMCSR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software
must check that the Flash programming is completed before initiating a new EEPROM write.
Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the
Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See
Support – Read-While-Write Self-Programming” on page 280
programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is
interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the
interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared
during all the steps to avoid these problems.
”Preventing EEPROM Corruption” on page 27
CC
is likely to rise or fall slowly on power-up/down. This causes the device for
”EEPROM Register Description” on page 28
310,
”Programming via the JTAG Interface” on page
Table 7-1 on page
for details on how to avoid problems in
for supplementary descrip-
24. A self-timing function,
ATmega169P
for details about Boot
respectively.
”Boot Loader
316, and
23
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