PIC24HJ64GP510-I/PT Microchip Technology, PIC24HJ64GP510-I/PT Datasheet - Page 185
![IC PIC MCU FLASH 32KX16 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC24HJ64GP510-I/PT
Manufacturer Part Number
PIC24HJ64GP510-I/PT
Description
IC PIC MCU FLASH 32KX16 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ64GP206-IPT.pdf
(292 pages)
3.PIC24HJ64GP206-IPT.pdf
(8 pages)
4.PIC24HJ64GP206-IPT.pdf
(20 pages)
5.PIC24HJ64GP206-IPT.pdf
(26 pages)
6.PIC24HJ128GP306-IPT.pdf
(288 pages)
Specifications of PIC24HJ64GP510-I/PT
Core Size
16-Bit
Program Memory Size
64KB (22K x 24)
Core Processor
PIC
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Controller Family/series
PIC24
No. Of I/o's
85
Ram Memory Size
8KB
Cpu Speed
40MIPS
No. Of Timers
13
No. Of Pwm Channels
8
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN, I2C, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Number Of Timers
13
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 32 Channel
A/d Bit Size
12 bit
A/d Channels Available
32
Height
1 mm
Length
12 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Width
12 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDAC164333 - MODULE SKT FOR PM3 100QFPDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24HJ64GP510-I/PT
Manufacturer:
Microchip
Quantity:
104
Company:
Part Number:
PIC24HJ64GP510-I/PT
Manufacturer:
MICROCHIP
Quantity:
455
Company:
Part Number:
PIC24HJ64GP510-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
18.6.2
There is a programmable prescaler with integral values
ranging from 1 to 64, in addition to a fixed divide-by-2
for clock generation. The time quantum (T
unit of time derived from the oscillator period and is
given by Equation 18-1.
EQUATION 18-1:
18.6.3
This part of the bit time is used to compensate physical
delay times within the network. These delay times con-
sist of the signal propagation time on the bus line and
the internal delay time of the nodes. The Prop Seg can
be programmed from 1 T
PRSEG<2:0> bits (CiCFG2<2:0>).
18.6.4
The phase segments are used to optimally locate the
sampling of the received bit within the transmitted bit
time. The sampling point is between Phase1 Seg and
Phase2 Seg. These segments are lengthened or short-
ened by resynchronization. The end of the Phase1 Seg
determines the sampling point within a bit period. The
segment is programmable from 1 T
Seg provides delay to the next transmitted data transi-
tion. The segment is programmable from 1 T
or it may be defined to be equal to the greater of
Phase1 Seg or the information processing time (2 T
The Phase1 Seg is initialized by setting bits
SEG1PH<2:0> (CiCFG2<5:3>) and Phase2 Seg is
initialized by setting SEG2PH<2:0> (CiCFG2<10:8>).
The following requirement must be fulfilled while setting
the lengths of the phase segments:
18.6.5
The sample point is the point of time at which the bus
level is read and interpreted as the value of that respec-
tive bit. The location is at the end of Phase1 Seg. If the
bit timing is slow and contains many T
specify multiple sampling of the bus line at the sample
point. The level determined by the CAN bus then corre-
sponds to the result from the majority decision of three
values. The majority samples are taken at the sample
point and twice before with a distance of T
CAN module allows the user to choose between sam-
pling three times at the same point or once at the same
point, by setting or clearing the SAM bit (CiCFG2<6>).
© 2006 Microchip Technology Inc.
Note:
Prop Seg + Phase1 Seg Phase2 Seg
PRESCALER SETTING
F
CANCKS = 0, then F
20 MHz.
PROPAGATION SEGMENT
PHASE SEGMENTS
SAMPLE POINT
T
CAN
Q
= 2 (BRP<5:0> + 1)/F
must not exceed 40 MHz. If
TIME QUANTUM FOR
CLOCK GENERATION
Q
to 8 T
CY
Q
CAN
Q
must not exceed
Q
to 8 T
, it is possible to
by setting the
Q
) is a fixed
Q
Q
. Phase2
Q
to 8 T
/2. The
Preliminary
Q
Q
).
,
Typically, the sampling of the bit should take place at
about 60-70% through the bit time, depending on the
system parameters.
18.6.6
To compensate for phase shifts between the oscillator
frequencies of the different bus stations, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. When an edge in
the transmitted data is detected, the logic will compare
the location of the edge to the expected time (Synchro-
nous Segment). The circuit will then adjust the values
of Phase1 Seg and Phase2 Seg. There are two
mechanisms used to synchronize.
18.6.6.1
Hard synchronization is only done whenever there is a
‘recessive’ to ‘dominant’ edge during bus Idle, indicat-
ing the start of a message. After hard synchronization,
the bit time counters are restarted with the Sync Seg.
Hard synchronization forces the edge which has
caused the hard synchronization to lie within the
synchronization segment of the restarted bit time. If a
hard synchronization is done, there will not be a
resynchronization within that bit time.
18.6.6.2
As a result of resynchronization, Phase1 Seg may be
lengthened or Phase2 Seg may be shortened. The
amount of lengthening or shortening of the phase
buffer segment has an upper boundary known as the
synchronization jump width, and is specified by the
SJW<1:0> bits (CiCFG1<7:6>). The value of the syn-
chronization jump width will be added to Phase1 Seg or
subtracted from Phase2 Seg. The resynchronization
jump width is programmable between 1 T
The following requirement must be fulfilled while setting
the SJW<1:0> bits:
Note:
Phase2 Seg > Synchronization Jump Width
SYNCHRONIZATION
In the register descriptions that follow, ‘i’ in
the register identifier denotes the specific
ECAN module (ECAN1 or ECAN2).
‘n’ in the register identifier denotes the
buffer, filter or mask number.
‘m’ in the register identifier denotes the
word number within a particular CAN data
field.
Hard Synchronization
Resynchronization
PIC24H
DS70175C-page 183
Q
and 4 T
Q
.