DSPIC30F4011-30I/ML Microchip Technology, DSPIC30F4011-30I/ML Datasheet - Page 110

• Manufacturer Part Number: DSPIC30F4011-30I/ML
• Description: IC DSPIC MCU/DSP 48K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4011-30I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F401130IML

dsPIC30F4011/4012
16.2
The module supports a basic framed SPI protocol in
Master or Slave mode. The control bit, FRMEN,
enables framed SPI support and causes the SS1 pin to
perform the frame synchronization pulse (FSYNC)
function. The control bit, SPIFSD, determines whether
FIGURE 16-1:
FIGURE 16-2:
DS70135G-page 110
SDO1
SCK1
SDI1
Framed SPI Support
SS1
MSb
PROCESSOR 1
SPI BLOCK DIAGRAM
SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
SPI Master
SS1 and
FSYNC
Shift Register
Control
Receive
(SPI1BUF)
(SPI1SR)
SPI1BUF
Read
bit 0
SPI1SR
LSb
Control
Clock
SDO1
SCK1
SDI1
Clock
Shift
SPI1BUF
Write
Transmit
Data Bus
Internal
Serial Clock
Select
Edge
the SS1 pin is an input or an output (i.e., whether the
module receives or generates the frame synchroniza-
tion pulse). The frame pulse is an active-high pulse for
a single SPI clock cycle. When frame synchronization
is enabled, the data transmission starts only on the
subsequent transmit edge of the SPI clock.
SDI1
SDO1
SCK1
Enable Master Clock
1, 2, 4, 6, 8
Secondary
Prescaler
MSb
Serial Input Buffer
Shift Register
PROCESSOR 2
(SPI1BUF)
(SPI1SR)
SPI Slave
© 2010 Microchip Technology Inc.
1, 4, 16, 64
Prescaler
Primary
LSb
F
CY