PIC18F252-I/SO Microchip Technology, PIC18F252-I/SO Datasheet - Page 122
PIC18F252-I/SO
Manufacturer Part Number
PIC18F252-I/SO
Description
IC MCU FLASH 16KX16 EE 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F242-ISO.pdf
(332 pages)
3.PIC18F242-ISO.pdf
(14 pages)
4.PIC18F242-ISO.pdf
(16 pages)
5.PIC18F242-ISO.pdf
(16 pages)
6.PIC18F242-ISO.pdf
(14 pages)
7.PIC18F452-EP.pdf
(332 pages)
Specifications of PIC18F252-I/SO
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
23
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
MSSP/SPI/I2C/PSP/USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
23
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
5-ch x 10-bit
Package
28SOIC W
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
PIC18F252-I/SOG
PIC18F252-I/SOG
PIC18F252I/SO
PIC18F252-I/SOG
PIC18F252I/SO
Available stocks
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- PIC16F616T-ISL PDF datasheet
- PIC18F242-ISO PDF datasheet #2
- PIC18F242-ISO PDF datasheet #3
- PIC18F242-ISO PDF datasheet #4
- PIC18F242-ISO PDF datasheet #5
- PIC18F242-ISO PDF datasheet #6
- PIC18F452-EP PDF datasheet #7
- Current page: 122 of 332
- Download datasheet (6Mb)
PIC18FXX2
14.4
In Compare mode, the 16-bit CCPR1 (CCPR2) register
value is constantly compared against either the TMR1
register pair value, or the TMR3 register pair value.
When a match occurs, the RC2/CCP1 (RC1/CCP2) pin
is:
• driven High
• driven Low
• toggle output (High to Low or Low to High)
• remains unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the
same time, interrupt flag bit CCP1IF (CCP2IF) is set.
14.4.1
The user must configure the CCPx pin as an output by
clearing the appropriate TRISC bit.
FIGURE 14-2:
DS39564C-page 120
Note:
RC2/CCP1 pin
RC1/CCP2 pin
Special Event Trigger will:
Compare Mode
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the PORTC
I/O data latch.
Reset Timer1 or Timer3, but not set Timer1 or Timer3 interrupt flag bit,
and set bit GO/DONE (ADCON0<2>)
which starts an A/D conversion (CCP2 only)
CCP PIN CONFIGURATION
Output Enable
Output Enable
TRISC<2>
TRISC<1>
COMPARE MODE OPERATION BLOCK DIAGRAM
Q
Q
R
R
S
S
Special Event Trigger
Special Event Trigger
CCP1CON<3:0>
CCP2CON<3:0>
Mode Select
Mode Select
Output
Output
Logic
Logic
Set Flag bit CCP1IF
Set Flag bit CCP2IF
Match
Match
14.4.2
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
14.4.3
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
14.4.4
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special trigger output of CCPx resets either the
TMR1 or TMR3 register pair. Additionally, the CCP2
Special Event Trigger will start an A/D conversion if the
A/D module is enabled.
Note:
T3CCP1
T3CCP2
TMR1H
The special event trigger from the CCP2
module will not set the Timer1 or Timer3
interrupt flag bits.
TIMER1/TIMER3 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
T3CCP2
TMR1L
CCPR1H CCPR1L
CCPR2H CCPR2L
Comparator
Comparator
© 2006 Microchip Technology Inc.
0
0
1
1
TMR3H
TMR3L
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