ATMEGA1284P-PU Atmel, ATMEGA1284P-PU Datasheet - Page 137
ATMEGA1284P-PU
Manufacturer Part Number
ATMEGA1284P-PU
Description
MCU AVR 128K ISP FLASH 40-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA644PA-PU.pdf
(581 pages)
2.ATMEGA644PA-PU.pdf
(32 pages)
3.ATMEGA1284PR231-AU.pdf
(380 pages)
4.ATMEGA1284P-MU.pdf
(20 pages)
Specifications of ATMEGA1284P-PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRAVEN, ATAVRRZUSBSTICK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
4KB
Ram Memory Size
16KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA1284P-PU
Manufacturer:
LUCENT
Quantity:
32
- ATMEGA644PA-PU PDF datasheet
- ATMEGA644PA-PU PDF datasheet #2
- ATMEGA1284PR231-AU PDF datasheet #3
- ATMEGA1284P-MU PDF datasheet #4
- Current page: 137 of 380
- Download datasheet (7Mb)
14.11.9
14.11.10 TIFR1 – Timer/Counter1 Interrupt Flag Register
8059D–AVR–11/09
TIMSK3 – Timer/Counter3 Interrupt Mask Register
• Bit 7:6 – Res: Reserved Bits
These bits are unused bits in the ATmega1284P, and will always read as zero.
• Bit 5 – ICIE3: Timer/Counter3, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see “Interrupts” on page 59) is executed when the ICF3 Flag, located in TIFR3, is set.
• Bit 4:3 – Res: Reserved Bits
These bits are unused bits in the ATmega1284P, and will always read as zero.
• Bit 2 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 59) is executed when the OCF3B Flag, located in
TIFR3, is set.
• Bit 1 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 59) is executed when the OCF3A Flag, located in
TIFR3, is set.
• Bit 0 – TOIE3: Timer/Counter3, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Overflow interrupt is enabled. The corresponding Interrupt Vector
(See Section “9.3” on page
• Bit 7:6 – Res: Reserved Bits
These bits are unused bits in the ATmega1284P, and will always read as zero.
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register
(ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 Flag is set when the coun-
ter reaches the TOP value.
Bit
(0x71)
Read/Write
Initial Value
Bit
0x16 (0x36)
Read/Write
Initial Value
R
R
7
–
0
7
–
0
R
6
–
0
R
6
–
0
53.) is executed when the TOV3 Flag, located in TIFR3, is set.
ICIE3
R/W
ICF1
R/W
5
0
5
0
R
4
–
0
R
4
–
0
R
3
–
0
R
3
–
0
OCIE3B
OCF1B
R/W
R/W
2
0
2
0
ATmega1284P
OCIE3A
OCF1A
R/W
R/W
1
0
1
0
TOIE3
TOV1
R/W
R/W
0
0
0
0
TIMSK3
TIFR1
137
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