ATMEGA1284P-PU Atmel, ATMEGA1284P-PU Datasheet - Page 46
![MCU AVR 128K ISP FLASH 40-PDIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA1284P-PU
Manufacturer Part Number
ATMEGA1284P-PU
Description
MCU AVR 128K ISP FLASH 40-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA644PA-PU.pdf
(581 pages)
2.ATMEGA644PA-PU.pdf
(32 pages)
3.ATMEGA1284PR231-AU.pdf
(380 pages)
4.ATMEGA1284P-MU.pdf
(20 pages)
Specifications of ATMEGA1284P-PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRAVEN, ATAVRRZUSBSTICK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
4KB
Ram Memory Size
16KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA1284P-PU
Manufacturer:
LUCENT
Quantity:
32
- ATMEGA644PA-PU PDF datasheet
- ATMEGA644PA-PU PDF datasheet #2
- ATMEGA1284PR231-AU PDF datasheet #3
- ATMEGA1284P-MU PDF datasheet #4
- Current page: 46 of 380
- Download datasheet (7Mb)
8.12.2
8.12.3
8.12.4
8059D–AVR–11/09
MCUCR – MCU Control Register
PRR1 – Power Reduction Register 1
PRR0 – Power Reduction Register 0
• Bit 6 – BODS: BOD Sleep
The BODS bit must be written to logic one in order to turn off BOD during sleep, see
on page
BODSE in MCUCR. To disable BOD in relevant sleep modes, both BODS and BODSE must first
be set to one. Then, to set the BODS bit, BODS must be set to one and BODSE must be set to
zero within four clock cycles.
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed
while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is
automatically cleared after three clock cycles.
• Bit 5 – BODSE: BOD Sleep Enable
BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable
is controlled by a timed sequence.
• Bit 7:1 - Res: Reserved
• Bit 0 - PRTIM3: Power Reduction Timer/Counter3
Writing a logic one to this bit shuts down the Timer/Counter3 module. When the Timer/Counter3
is enabled, operation will continue like before the shutdown.
• Bit 7 - PRTWI: Power Reduction TWI
Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When
waking up the TWI again, the TWI should be re initialized to ensure proper operation.
• Bit 6 - PRTIM2: Power Reduction Timer/Counter2
Writing a logic one to this bit shuts down the Timer/Counter2 module in synchronous mode (AS2
is 0). When the Timer/Counter2 is enabled, operation will continue like before the shutdown.
Bit
0x35 (0x55)
Read/Write
Initial Value
Bit
(0x65)
Read/Write
Initial Value
Bit
(0x64)
Read/Write
Initial Value
40. Writing to the BODS bit is controlled by a timed sequence and an enable bit,
PRTWI
R/W
JTD
R/W
7
0
R
7
0
7
0
-
PRTIM2
R/W
BODS
6
0
R
R
6
0
6
0
-
PRTIM0
R/W
BODSE
5
0
R
5
0
R
-
5
0
PRUSART1
R/W
4
0
PUD
R/W
R
4
0
-
0
4
PRTIM1
R/W
R
3
0
-
3
0
R
3
–
0
PRSPI
R/W
2
0
R
R
2
0
2
–
0
-
ATmega1284P
PRUSART0
IVSEL
R/W
R/W
1
0
1
0
R
1
0
-
IVCE
R/W
PRTIM3
PRADC
0
0
R/W
R/W
0
0
0
0
Table 8-1
MCUCR
PRR1
PRR0
46
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