PIC32MX360F256L-80I/PT Microchip Technology, PIC32MX360F256L-80I/PT Datasheet - Page 478

• Manufacturer Part Number: PIC32MX360F256L-80I/PT
• Description: IC PIC MCU FLASH 256K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F256L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 256KB (256K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX FAMILY
EXAMPLE 21-2:
21.2.3
In order to perform a write to any of the RTCC Time reg-
isters, the RTCWREN bit (RTCCON<3>) must be set.
Setting of the RTCWREN bit is only allowed once the
device level unlocking sequence has been executed.
The unlocking sequence is as follows:
1.
2.
3.
EXAMPLE 21-3:
DS61143B-page 476
// assume interrupts are disabled
// assume the DMA controller is suspended
// assume the device is locked
// can resume the DMA controller activity
// can re-enable interrupts
/*
*/
Note:
Suspend or disable all initiators that can access
the peripheral bus and interrupt the unlock
sequence. (i.e., DMA and Interrupts).
Store 0xAA996655 to the SYSKEY register.
Store 0x556699AA to the SYSKEY register.
// starting critical sequence
SYSKEY = 0xaa996655;
SYSKEY = 0x556699aa;
RTCCONSET = 0x8;
// end critical sequence
SYSKEY = 0x33333333;
The following code example will update the RTCC time and date.
// assume RTCC write is enabled i.e. RTCWREN (RTCCON<3>) =1;
unsigned long time=0x04153300;// set time to 04 hr, 15 min, 33 sec
unsigned long date=0x06102705;// set date to Friday 27 Oct 2006
// disable interrupts, critical section follows
__asm__ __volatile__ (“di”);
while((RTCCON&0x4)!=0);
RTCTIME=time;
RTCDATE=date;
// restore interrupts, critical section ended
__asm__ __volatile__ (“ei”);
// can disable the RTCC write
WRITE LOCK
To avoid accidental writes to the RTCC time values, it is recommended that the RTCWREN bit
(RTCCON<3>) is kept clear at any other time.
UPDATING THE RTCC TIME USING THE RTCSYNC WINDOW
WRITE UNLOCK SEQUENCE
// write first unlock key to SYSKEY
// write second unlock key to SYSKEY
// set RTCWREN in RTCCONSET
// perform device re-lock
// wait for not RTCSYNC
// safe to update the time
// update the date
Advance Information
implementation of the write unlock operation.
4.
5.
6.
Note that steps 2 through 4 must be followed exactly to
unlock RTCC write operations. If the sequence is not
followed exactly, the RTCWREN bit will not be set.
Refer
Set RTCWREN bit into the RTCCON register.
Perform the device relock by writing a dummy
value to the SYSKEY register.
Re-enable DMA and interrupts.
to
Example 21-3
© 2008 Microchip Technology Inc.
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