PIC18F4220-I/ML Microchip Technology, PIC18F4220-I/ML Datasheet - Page 22
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PIC18F4220-I/ML
Manufacturer Part Number
PIC18F4220-I/ML
Description
IC MCU FLASH 2KX16 EEPROM 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F1320-ISS.pdf
(36 pages)
3.PIC18F2220-ISO.pdf
(394 pages)
4.PIC18F2220-ISO.pdf
(6 pages)
5.PIC18F2220-ISO.pdf
(6 pages)
6.PIC18F2220-ISO.pdf
(8 pages)
7.PIC18F2220-ISO.pdf
(6 pages)
8.PIC18F2220-ISO.pdf
(6 pages)
Specifications of PIC18F4220-I/ML
Core Size
8-Bit
Program Memory Size
4KB (2K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN444-1001 - DEMO BOARD FOR PICMICRO MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
PIC18FX220/X320
4.3
The verify step involves reading back the code memory
space and comparing it against the copy held in the
programmer’s buffer. Memory reads occur a single byte
at a time, so two bytes must be read to compare
against the word in the programmer’s buffer. Refer to
Section 4.2 “Read Code Memory, ID Locations and
Configuration Bits” for implementation details of
reading code memory.
FIGURE 4-4:
4.4
A configuration address may be read and output on
PGD via the 4-bit command, ‘1001’. Configuration data
is read and written in a byte-wise fashion, so it is not
necessary to merge two bytes into a word prior to a
compare. The result may then be immediately
compared to the appropriate configuration data in the
programmer’s memory for verification. Refer to
Section 4.2 “Read Code Memory, ID Locations and
Configuration Bits” for implementation details of
reading configuration data.
DS39592F-page 22
Verify Code Memory and
ID Locations
Verify Configuration Bits
No
Read High Byte
Read Low Byte
Set Pointer = 0
word = expect
code memory
VERIFY CODE MEMORY FLOW
verified?
data?
Does
Start
All
Yes
Yes
No
Failure,
Report
Error
The Table Pointer must be manually set to 200000h
(base address of the ID locations). The post-increment
feature of the table read 4-bit command may not be
used to increment the Table Pointer to 200000h. The
post-increment feature may then be used to increment
to 200001h, 200002h, etc.
4.5
A data EEPROM address may be read via a sequence
of core instructions (4-bit command, ‘0000’) and then
output on PGD via the 4-bit command, ‘0010’ (Shift Out
Data Holding register). The result may then be
immediately compared to the appropriate data in the
programmer’s memory for verification. Refer to
Section 4.1 “Read Data EEPROM Memory” for
implementation details of reading data EEPROM.
No
Verify Data EEPROM
Set Pointer = 200000h
Read High Byte
Read Low Byte
word = expect
ID locations
verified?
data?
Does
Done
All
Yes
Yes
2010 Microchip Technology Inc.
No
Failure,
Report
Error