PIC18F4320-I/PT Microchip Technology, PIC18F4320-I/PT Datasheet - Page 2

• Manufacturer Part Number: PIC18F4320-I/PT
• Description: IC MCU FLASH 4KX16 A/D 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4320-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2220/2320/4220/4320
2. Module: MSSP (All I
DS80396B-page 2
The Buffer Full flag bit (BF) of the SSPSTAT regis-
ter (SSPSTAT<0>) may be inadvertently cleared,
even when the SSPBUF register has not been
read. This will occur only when the following two
conditions occur simultaneously:
• The four Least Significant bits of the BSR
• Any instruction that contains C9h in its 8 Least
Work around
Identified work arounds will involve setting the
contents of BSR<3:0> to some value other than
0Fh.
In addition to those proposed below, other solutions
may exist.
1. When developing or modifying code, keep
2. If accessing a part of Bank 15 is required and
3. If pointing the BSR to Bank 15 is unavoidable,
Date Codes that pertain to this issue:
All engineering and production devices.
register are equal to 0Fh (BSR<3:0> = 1111)
and
Significant bits (i.e., register file addresses,
literal data, address offsets, etc.) is executed.
these guidelines in mind:
• Assign 12-bit addresses to all variables.
• Do not set the BSR to point to Bank 15
• Allow the assembler to manipulate the
the use of Access Banking is not possible,
consider using indirect addressing.
review the absolute file listing. Verify that no
instructions contain C9h in the 8 Least Signifi-
cant bits while the BSR points to Bank 15
(BSR = 0Fh).
This allows the assembler to know when
Access Banking can be used.
(BSR = 0Fh).
Access bit present in most instructions.
Accessing the SFRs in Bank 15 will be done
through the Access Bank. Continue to use
the BSR to select all GPR Banks.
2
C™ and SPI Modes)
3. Module: MSSP (SPI, Slave Mode)
In its current implementation, the SS (Slave
Select) control signal generated by an external
master processor may not be successfully recog-
nized by the PIC
Slave Select mode (SSPM3:SSPM0 = 0100). In
particular, it has been observed that faster transi-
tions (those with shorter fall times) are more likely
to be missed than slower transitions.
Work around
Insert a series resistor between the source of the
SS signal and the corresponding SS input line of
the microcontroller. The value of the resistor is
dependent on both the application system’s
characteristics and process variations between
microcontrollers. Experimentation and thorough
testing is encouraged.
This is a recommended solution; others may exist.
Date Codes that pertain to this issue:
All engineering and production devices.
®
© 2009 Microchip Technology Inc.
microcontroller operating in