AT89C51IC2-RLTUM Atmel, AT89C51IC2-RLTUM Datasheet - Page 25

• Manufacturer Part Number: AT89C51IC2-RLTUM
• Description: IC 8051 MCU FLASH 32K 44VQFP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51IC2-RLTUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 3 bit
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Dual Data Pointer
Register
Figure 7. Use of Dual Pointer
4301D–8051–02/08
7
AUXR1(A2H)
DPS
0
The additional data pointer can be used to speed up code execution and reduce code
size.
The dual DPTR structure is a way by which the chip will specify the address of an exter-
nal data memory location. There are two 16-bit DPTR registers that address the external
memory, and a single bit called DPS = AUXR1.0 (see Table 21) that allows the program
code to switch between them (Refer to Figure 7).
Table 21. AUXR1 register
AUXR1- Auxiliary Register 1(0A2h)
Reset Value: XXXX XX0X0b
Not bit addressable
Note:
Number
Bit
7
-
7
6
5
4
3
2
1
0
*Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
DPH(83H) DPL(82H)
Mnemonic Description
ENBOOT
DPS
GF3
Bit
6
-
0
-
-
-
-
DPTR1
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Enable Boot Flash
Cleared to disable boot rom.
Set to map the boot rom between F800h - 0FFFFh.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
This bit is a general purpose user flag.*
Always cleared.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Data Pointer Selection
Cleared to select DPTR0.
Set to select DPTR1.
ENBOOT
DPTR0
5
4
-
GF3
3
External Data Memory
2
0
1
-
DPS
0
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