ATMEGA645V-8AU Atmel, ATMEGA645V-8AU Datasheet - Page 70
![IC AVR MCU FLASH 64K 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA645V-8AU
Manufacturer Part Number
ATMEGA645V-8AU
Description
IC AVR MCU FLASH 64K 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA325-16MU.pdf
(362 pages)
Specifications of ATMEGA645V-8AU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SPI, UART, USI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
54
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AVR MEGA
No. Of I/o's
54
Eeprom Memory Size
2KB
Ram Memory Size
4KB
Cpu Speed
8MHz
No. Of Timers
3
Rohs Compliant
Yes
Data Rom Size
2 KB
Height
1 mm
Length
14 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
14 mm
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
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2570M–AVR–04/11
Table 13-4
shown in
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
Table 13-4.
Table 13-5.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Figure 13-5 on page
and
Overriding Signals for Alternate Functions in PB7:PB4
Overriding Signals for Alternate Functions in PB3:PB0
PB7/OC2A/
PCINT15
0
0
0
0
OC2A ENABLE
OC2A
–
PCINT15 •
PCIE1
1
PCINT15 INPUT
–
PB3/MISO/
PCINT11
SPE • MSTR
PORTB3 • PUD
SPE • MSTR
0
SPE • MSTR
SPI SLAVE
OUTPUT
–
PCINT11 •
PCIE1
1
PCINT11 INPUT
SPI MSTR
INPUT
–
Table 13-5
relate the alternate functions of Port B to the overriding signals
66. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
PB6/OC1B/
PCINT14
0
0
0
0
OC1B ENABLE
OC1B
–
PCINT14 •
PCIE1
1
PCINT14 INPUT
–
PB2/MOSI/
PCINT10
SPE • MSTR
PORTB2 • PUD
SPE • MSTR
0
SPE • MSTR
SPI MSTR
OUTPUT
–
PCINT10 •
PCIE1
1
PCINT10 INPUT
SPI SLAVE
INPUT
–
ATmega325/3250/645/6450
PB5/OC1A/
PCINT13
0
0
0
0
OC1A ENABLE
OC1A
–
PCINT13 •
PCIE1
1
PCINT13 INPUT
–
PB1/SCK/
PCINT9
SPE • MSTR
PORTB1 • PUD
SPE • MSTR
0
SPE • MSTR
SCK OUTPUT
–
PCINT9 • PCIE1
1
PCINT9 INPUT
SCK INPUT
–
PB4/OC0A/
PCINT12
0
0
0
0
OC0A ENABLE
OC0A
–
PCINT12 •
PCIE1
1
PCINT12 INPUT
–
PB0/SS/
PCINT8
SPE • MSTR
PORTB0 • PUD
SPE • MSTR
0
0
0
–
PCINT8 • PCIE1
1
PCINT8 INPUT
SPI SS
–
70
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