PIC17C42A-16/P Microchip Technology, PIC17C42A-16/P Datasheet - Page 76

• Manufacturer Part Number: PIC17C42A-16/P
• Description: IC MCU OTP 2KX16 PWM 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C42A-16/P

• Core Size: 8-Bit
• Program Memory Size: 4KB (2K x 16)
• Core Processor: PIC
• Speed: 16MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 232 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC17
• No. Of I/o's: 33
• Ram Memory Size: 232Byte
• Cpu Speed: 16MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Embedded Interface Type: USART
• Rohs Compliant: Yes
• Processor Series: PIC17C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 232 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA17XP401 - DEVICE ADAPTER FOR PIC17C42AAC174001 - MODULE SKT PROMATEII 40DIP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

PIC17C4X
12.1.3.1
The period of the PWM1 output is determined by
Timer1 and its period register (PR1). The period of the
PWM2 output can be software configured to use either
Timer1 or Timer2 as the time-base. When TM2PW2 bit
(PW2DCL<5>) is clear, the time-base is determined by
TMR1 and PR1. When TM2PW2 is set, the time-base
is determined by Timer2 and PR2.
Running two different PWM outputs on two different
timers allows different PWM periods. Running both
PWMs from Timer1 allows the best use of resources by
freeing Timer2 to operate as an 8-bit timer. Timer1 and
Timer2 can not be used as a 16-bit timer if either PWM
is being used.
The PWM periods can be calculated as follows:
The duty cycle of PWMx is determined by the 10-bit
value DCx<9:0>. The upper 8-bits are from register
PWxDCH and the lower 2-bits are from PWxDCL<7:6>
(PWxDCH:PWxDCL<7:6>). Table 12-3 shows the
maximum PWM frequency (F
the period register.
The number of bits of resolution that the PWM can
achieve depends on the operation frequency of the
device as well as the PWM frequency (F
Maximum PWM resolution (bits) for a given PWM fre-
quency:
The PWMx duty cycle is as follows:
where
PWxDCH:PWxDCL.
If DCx = 0, then the duty cycle is zero. If PRx =
PWxDCH, then the PWM output will be low for one to
four Q-clock (depending on the state of the
PWxDCL<7:6> bits). For a Duty Cycle to be 100%, the
PWxDCH value must be greater then the PRx value.
The duty cycle registers for both PWM outputs are dou-
ble buffered. When the user writes to these registers,
they are stored in master latches. When TMR1 (or
TMR2) overflows and a new PWM period begins, the
master latch values are transferred to the slave latches
and the PWMx pin is forced high.
DS30412C-page 76
Note:
period of PWM1 =[(PR1) + 1] x 4T
period of PWM2 =[(PR1) + 1] x 4T
PWMx Duty Cycle = (DCx) x T
DCx
PWM PERIODS
For PW1DCH, PW1DCL, PW2DCH and
PW2DCL registers, a write operation
writes to the "master latches" while a read
operation reads the "slave latches". As a
result, the user may not read back what
was just written to the duty cycle registers.
=
represents
log
log (2)
(
[(PR2) + 1] x 4T
F
F
PWM
OSC
the
PWM
)
10-bit
) given the value in
bits
OSC
OSC
OSC
OSC
PWM
value
or
).
from
The user should also avoid any "read-modify-write"
operations on the duty cycle registers, such as: ADDWF
PW1DCH . This may cause duty cycle outputs that are
unpredictable.
TABLE 12-3:
12.1.3.2
The PWM module makes use of TMR1 or TMR2 inter-
rupts. A timer interrupt is generated when TMR1 or
TMR2 equals its period register and is cleared to zero.
This interrupt also marks the beginning of a PWM
cycle. The user can write new duty cycle values before
the timer roll-over. The TMR1 interrupt is latched into
the TMR1IF bit and the TMR2 interrupt is latched into
the TMR2IF bit. These flags must be cleared in soft-
ware.
12.1.3.3
The PWMs will operate regardless of the clock source
of the timer. The use of an external clock has ramifica-
tions that must be understood. Because the external
TCLK12 input is synchronized internally (sampled once
per instruction cycle), the time TCLK12 changes to the
time the timer increments will vary by as much as T
(one instruction cycle). This will cause jitter in the duty
cycle as well as the period of the PWM output.
This jitter will be T
chronized with the processor clock. Use of one of the
PWM outputs as the clock source to the TCLKx input,
will supply a synchronized clock.
In general, when using an external clock source for
PWM, its frequency should be much less than the
device frequency (Fosc).
PRx Value
High
Resolution
Standard
Resolution
Frequency
PWM
PWM INTERRUPTS
EXTERNAL CLOCK SOURCE
0xFF
10-bit
8-bit
24.4
PWM FREQUENCY vs.
RESOLUTION AT 25 MHz
CY
, unless the external clock is syn-
0x7F 0x5F
9-bit
7-bit
48.8 65.104
Frequency (kHz)
1996 Microchip Technology Inc.
8.5-bit
6.5-bit
0x3F
8-bit
6-bit
97.66
0x0F
6-bit
4-bit
390.6
CY