PIC18F4585-I/PT Microchip Technology, PIC18F4585-I/PT Datasheet - Page 9

• Manufacturer Part Number: PIC18F4585-I/PT
• Description: IC MCU FLASH 24KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4585-I/PT

• Core Size: 8-Bit
• Program Memory Size: 48KB (24K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3.25KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPI3-DB18F4680 - BOARD DAUGHTER ICEPIC3AC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

28. Module: MSSP
EXAMPLE 5:
29. Module: Reset
© 2007 Microchip Technology Inc.
When the MSSP is configured for SPI mode, the
Buffer Full Status bit, BF (SSPSTAT<0>), should
not be polled in software to determine when the
transfer is complete.
Work around
Copy the SSPSTAT register into a variable and
perform the bit test on the variable. In Example 5,
SSPSTAT is copied into the working register
where the bit test is performed.
A second option is to poll the Master Synchronous
Serial Port Interrupt Flag bit, SSPIF (PIR1<3>).
This bit can be polled and will set when the transfer
is complete.
Date Codes that pertain to this issue:
All engineering and production devices.
This version of silicon does not support the func-
tionality described in Note 1 of parameter D002 in
Section 27.1
Voltage” of the Device Data Sheet. The RAM
content may be altered during a Reset event if the
following conditions are met.
• Device is accessing RAM.
• Asynchronous Reset (i.e., WDT, BOR or MCLR
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
loop_MSB:
occurs when a write operation is being
executed (start of a Q4 cycle).
MOVF
BTFSS
BRA
“DC
SSPSTAT, W
WREG, BF
loop_MSB
Characteristics:
PIC18F2585/2680/4585/4680
Supply
30. Module: ECAN™ Technology
31. Module: ECAN™ Technology
32. Module: ECAN™ Technology
Under specific conditions, the first five bits of a
transmitted identifier may not match the value in
the Transmit Buffer ID register, TXBnSIDH. The
following conditions must exist for the corruption to
occur:
1. A transmit message must be pending.
2. The ECAN module must detect a Start-Of-
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
The Error Interrupt Flag, ERRIF (PIR3<5>), may
not be able to clear in software after either of the
following counter registers exceeds 127.
• Transmit Error Counter Register TXERRCNT
• Receive Error Counter Register RXERRCNT
Work around
Monitor the EWARN (COMSTAT<0>) bit to deter-
mine if either the TXERRCNT or the RXERRCNT
exceeds 95 and clear the ERRIF flag before either
counter reaches 127.
Date Codes that pertain to this issue:
All engineering and production devices.
Following an error on the bus, the ECAN module is
unable to switch from Listen Only mode directly to
Configuration mode.
Work around
Use the REQOP (CANCON<7:5>) bits to select
Normal mode as an intermediate step when
switching from Listen Only mode to Configuration
mode.
Date Codes that pertain to this issue:
All engineering and production devices.
Frame (SOF) in the third bit of interframe
space.
DS80202G-page 9