PIC18LF2585-I/SO Microchip Technology, PIC18LF2585-I/SO Datasheet - Page 163
![IC MCU FLASH 24KX16 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18LF2585-I/SO
Manufacturer Part Number
PIC18LF2585-I/SO
Description
IC MCU FLASH 24KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F4585-IPT.pdf
(482 pages)
4.PIC18F4585-IPT.pdf
(14 pages)
5.PIC18F4585-IPT.pdf
(8 pages)
6.PIC18F4585-IPT.pdf
(12 pages)
7.PIC18F4585-IPT.pdf
(4 pages)
Specifications of PIC18LF2585-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
I2C, SPI, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
28
Number Of Timers
1 x 8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163011, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC18LF2585-I/SOR
PIC18LF2585-I/SOR
PIC18LF2585-I/SOR
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F4585-IPT PDF datasheet #3
- PIC18F4585-IPT PDF datasheet #4
- PIC18F4585-IPT PDF datasheet #5
- PIC18F4585-IPT PDF datasheet #6
- PIC18F4585-IPT PDF datasheet #7
- Current page: 163 of 482
- Download datasheet (9Mb)
14.2
Timer3 can be configured for 16-bit reads and writes
(see Figure 14-2). When the RD16 control bit
(T3CON<7>) is set, the address for TMR3H is mapped
to a buffer register for the high byte of Timer3. A read
from TMR3L will load the contents of the high byte of
Timer3 into the Timer3 High Byte Buffer register. This
provides the user with the ability to accurately read all
16 bits of Timer1 without having to determine whether
a read of the high byte, followed by a read of the low
byte, has become invalid due to a rollover between
reads.
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bits to both the high and low bytes of Timer3 at once.
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register.
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
14.3
The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting the T1OSCEN (T1CON<3>) bit. To use it as the
Timer3 clock source, the TMR3CS bit must also be set.
As previously noted, this also configures Timer3 to
increment on every rising edge of the oscillator source.
The Timer1 oscillator is described in Section 12.0
“Timer1 Module”.
TABLE 14-1:
© 2007 Microchip Technology Inc.
INTCON
PIR2
PIE2
IPR2
TMR3L
TMR3H
T1CON
T3CON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
Note 1:
Name
2:
Timer3 16-Bit Read/Write Mode
Using the Timer1 Oscillator as the
Timer3 Clock Source
Timer3 Register, Low Byte
Timer3 Register, High Byte
These bits are available in PIC18F4X8X devices only.
These bits are available in PIC18F4X8X devices and reserved in PIC18F2X8X devices.
GIE/GIEH PEIE/GIEL
OSCFIF
OSCFIE
OSCFIP
RD16
RD16
Bit 7
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
T3ECCP1
CMIE
CMIP
CMIF
T1RUN
Bit 6
(2)
(2)
(2)
(1)
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
T3CKPS1 T3CKPS0 T3CCP1
TMR0IE
Bit 5
—
—
—
PIC18F2585/2680/4585/4680
INT0IE
Preliminary
Bit 4
EEIF
EEIE
EEIP
BCLIE
BCLIP
BCLIF
RBIE
14.4
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in the interrupt flag bit, TMR3IF
(PIR2<1>). This interrupt can be enabled or disabled
by setting or clearing the Timer3 Interrupt Enable bit,
TMR3IE (PIE2<1>).
14.5
If the ECCP1 module is configured to generate a
special event
(ECCP1M3:ECCP1M0 = 1011), this signal will reset
Timer3. It will also start an A/D conversion if the A/D
module is enabled (see Section 15.3.4 “Special
Event Trigger” for more information.).
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the ECCPR1H:ECCPR1L register
pair effectively becomes a period register for Timer3.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
In the event that a write to Timer3 coincides with a
special event trigger from a CCP1 module, the write will
take precedence.
Bit 3
Note:
(1)
Timer3 Interrupt
Resetting Timer3 Using the
ECCP1 Special Event Trigger
T3SYNC
TMR0IF
HLVDIF
HLVDIE
HLVDIP
The special event triggers from the
ECCP1 module will not set the TMR3IF
interrupt flag bit (PIR1<0>).
Bit 2
trigger
TMR1CS
TMR3CS
TMR3IF
TMR3IE ECCP1IE
TMR3IP ECCP1IP
INT0IF
Bit 1
in
ECCP1IF
TMR1ON
TMR3ON
Compare
DS39625C-page 161
RBIF
Bit 0
(2)
(2)
(2)
on page
Values
Reset
mode
49
51
52
51
51
51
50
51
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