PIC18LF2585-I/SO Microchip Technology, PIC18LF2585-I/SO Datasheet - Page 332
![IC MCU FLASH 24KX16 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18LF2585-I/SO
Manufacturer Part Number
PIC18LF2585-I/SO
Description
IC MCU FLASH 24KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F4585-IPT.pdf
(482 pages)
4.PIC18F4585-IPT.pdf
(14 pages)
5.PIC18F4585-IPT.pdf
(8 pages)
6.PIC18F4585-IPT.pdf
(12 pages)
7.PIC18F4585-IPT.pdf
(4 pages)
Specifications of PIC18LF2585-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
I2C, SPI, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
28
Number Of Timers
1 x 8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163011, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC18LF2585-I/SOR
PIC18LF2585-I/SOR
PIC18LF2585-I/SOR
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F4585-IPT PDF datasheet #3
- PIC18F4585-IPT PDF datasheet #4
- PIC18F4585-IPT PDF datasheet #5
- PIC18F4585-IPT PDF datasheet #6
- PIC18F4585-IPT PDF datasheet #7
- Current page: 332 of 482
- Download datasheet (9Mb)
PIC18F2585/2680/4585/4680
23.7.3
When configured for Mode 2, two of the dedicated
receive buffers in combination with one or more
programmable transmit/receive buffers, are used to
create a maximum of an 8 buffer deep FIFO buffer. In
this mode, there is no direct correlation between filters
and receive buffer registers. Any filter that has been
enabled can generate an acceptance. When a
message has been accepted, it is stored in the next
available receive buffer register and an internal write
pointer is incremented. The FIFO can be a maximum of
8 buffers deep. The entire FIFO must consist of contig-
uous receive buffers. The FIFO head begins at RXB0
buffer and its tail spans toward B5. The maximum
length of the FIFO is limited by the presence or
absence of the first transmit buffer starting from B0. If a
buffer is configured as a transmit buffer, the FIFO
length is reduced accordingly. For instance, if B3 is
configured as a transmit buffer, the actual FIFO will
consist of RXB0, RXB1, B0, B1 and B2, a total of 5
buffers. If B0 is configured as a transmit buffer, the
FIFO length will be 2. If none of the programmable
buffers are configured as a transmit buffer, the FIFO will
be 8 buffers deep. A system that requires more transmit
buffers should try to locate transmit buffers at the very
end of B0-B5 buffers to maximize available FIFO
length.
When a message is received in FIFO mode, the inter-
rupt flag code bits (EICODE<4:0>) in the CANSTAT
register will have a value of ‘10000’, indicating the
FIFO has received a message. FIFO Pointer bits,
FP<3:0> in the CANCON register, point to the buffer
that contains data not yet read. The FIFO pointer bits,
in this sense, serve as the FIFO read pointer. The user
should use FP bits and read corresponding buffer data.
When receive data is no longer needed, the RXFUL bit
in the current buffer must be cleared, causing FP<3:0>
to be updated by the module.
To determine whether FIFO is empty or not, the user
may use FP<3:0> bits to access the RXFUL bit in the
current buffer. If RXFUL is cleared, the FIFO is consid-
ered to be empty. If it is set, the FIFO may contain one
or more messages. In Mode 2, the module also pro-
vides a bit called FIFO High Water Mark (FIFOWM) in
the ECANCON register. This bit can be used to cause
an interrupt whenever the FIFO contains only one or
four empty buffers. The FIFO high water mark interrupt
can serve as an early warning to a full FIFO condition.
DS39625C-page 330
ENHANCED FIFO MODE
Preliminary
23.7.4
The CAN module can be programmed to generate a
time-stamp for every message that is received. When
enabled, the module generates a capture signal for
CCP1, which in turn captures the value of either Timer1
or Timer3. This value can be used as the message
time-stamp.
To use the time-stamp capability, the CANCAP bit
(CIOCAN<4>) must be set. This replaces the capture
input for CCP1 with the signal generated from the CAN
module. In addition, CCP1CON<3:0> must be set to
‘0011’ to enable the CCP special event trigger for CAN
events.
23.8
The message acceptance filters and masks are used to
determine if a message in the Message Assembly
Buffer should be loaded into any of the receive buffers.
Once a valid message has been received into the MAB,
the identifier fields of the message are compared to the
filter values. If there is a match, that message will be
loaded into the appropriate receive buffer. The filter
masks are used to determine which bits in the identifier
are examined with the filters. A truth table is shown
below in Table 23-2 that indicates how each bit in the
identifier is compared to the masks and filters to deter-
mine if a message should be loaded into a receive
buffer. The mask essentially determines which bits to
apply the acceptance filters to. If any mask bit is set to
a zero, then that bit will automatically be accepted
regardless of the filter bit.
TABLE 23-2:
In Mode 0, acceptance filters RXF0 and RXF1 and filter
mask RXM0 are associated with RXB0. Filters RXF2,
RXF3, RXF4 and RXF5 and mask RXM1 are
associated with RXB1.
Legend: x = don’t care
Mask
bit n
0
1
1
1
1
Message Acceptance Filters
and Masks
TIME-STAMPING
Filter
bit n
x
0
0
1
1
FILTER/MASK TRUTH TABLE
© 2007 Microchip Technology Inc.
Message
Identifier
bit n001
x
0
1
0
1
Accept or
Reject
Accept
Accept
Accept
Reject
Reject
bit n
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