PIC18C452-I/L Microchip Technology, PIC18C452-I/L Datasheet - Page 147
![IC MCU OTP 16KX16 A/D 44PLCC](/photos/6/63/66325/150-44-plcc_sml.jpg)
PIC18C452-I/L
Manufacturer Part Number
PIC18C452-I/L
Description
IC MCU OTP 16KX16 A/D 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C242-ISO.pdf
(305 pages)
4.PIC18C242-ISO.pdf
(12 pages)
Specifications of PIC18C452-I/L
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
33
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Controller Family/series
PIC18
No. Of I/o's
34
Ram Memory Size
1.5KB
Cpu Speed
40MHz
No. Of Timers
4
Package
44PLCC
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
34
Interface Type
I2C/SPI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
4
Processor Series
PIC18C
Core
PIC
Data Ram Size
1.5 KB
Maximum Clock Frequency
40 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
ICE2000, DM163022, DV164136
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3DB18C452 - BOARD DAUGHTER ICEPIC3AC164309 - MODULE SKT FOR PM3 44PLCC444-1001 - DEMO BOARD FOR PICMICRO MCUDVA16XL441 - ADAPTER DEVICE ICE 44PLCCDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C452-I/L
Manufacturer:
MICROCHIP
Quantity:
58
Company:
Part Number:
PIC18C452-I/L
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C242-ISO PDF datasheet #3
- PIC18C242-ISO PDF datasheet #4
- Current page: 147 of 305
- Download datasheet (6Mb)
14.4.16.1
During a START condition, a bus collision occurs if:
a)
b)
During a START condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the START condition is aborted,
• the BCLIF flag is set, and
• the MSSP module is reset to its IDLE state
The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data '1' during the START condition.
FIGURE 14-24:
(Figure 14-24).
2001 Microchip Technology Inc.
SDA
SCL
SEN
BCLIF
S
SSPIF
SDA or SCL are sampled low at the beginning of
the START condition (Figure 14-24).
SCL is sampled low before SDA is asserted low
(Figure 14-25).
Bus Collision During a START
Condition
BUS COLLISION DURING START CONDITION (SDA ONLY)
condition if SDA = 1, SCL=1
Set SEN, enable START
SDA sampled low before
START condition.
S bit and SSPIF set because
SDA = 0, SCL = 1.
. Set BCLIF,
SDA goes low before the SEN bit is set.
S bit and SSPIF set because
SDA = 0, SCL = 1.
Set BCLIF.
SSPIF and BCLIF are
cleared in software
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 14-26). If, however, a '1' is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to 0, and during this time, if the SCL pins
are sampled as '0', a bus collision does not occur. At
the end of the BRG count, the SCL pin is asserted low.
Note:
SEN cleared automatically because of bus collision.
SSP module reset into idle state.
The reason that bus collision is not a factor
during a START condition, is that no two
bus masters can assert a START condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision, because the two masters must be
allowed to arbitrate the first address follow-
ing the START condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
START, or STOP conditions.
SSPIF and BCLIF are
cleared in software
PIC18CXX2
DS39026C-page 145
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