PIC18C452-I/L Microchip Technology, PIC18C452-I/L Datasheet - Page 52
![IC MCU OTP 16KX16 A/D 44PLCC](/photos/6/63/66325/150-44-plcc_sml.jpg)
PIC18C452-I/L
Manufacturer Part Number
PIC18C452-I/L
Description
IC MCU OTP 16KX16 A/D 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C242-ISO.pdf
(305 pages)
4.PIC18C242-ISO.pdf
(12 pages)
Specifications of PIC18C452-I/L
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
33
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Controller Family/series
PIC18
No. Of I/o's
34
Ram Memory Size
1.5KB
Cpu Speed
40MHz
No. Of Timers
4
Package
44PLCC
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
34
Interface Type
I2C/SPI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
4
Processor Series
PIC18C
Core
PIC
Data Ram Size
1.5 KB
Maximum Clock Frequency
40 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
ICE2000, DM163022, DV164136
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3DB18C452 - BOARD DAUGHTER ICEPIC3AC164309 - MODULE SKT FOR PM3 44PLCC444-1001 - DEMO BOARD FOR PICMICRO MCUDVA16XL441 - ADAPTER DEVICE ICE 44PLCCDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C452-I/L
Manufacturer:
MICROCHIP
Quantity:
58
Company:
Part Number:
PIC18C452-I/L
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18CXX2
4.12
Indirect addressing is a mode of addressing data mem-
ory, where the data memory address in the instruction
is not fixed. An FSR register is used as a pointer to the
data memory location that is to be read or written. Since
this pointer is in RAM, the contents can be modified by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 4-9
shows the operation of indirect addressing. This shows
the moving of the value to the data memory address,
specified by the value of the FSR register.
Indirect addressing is possible by using one of the
INDF registers. Any instruction using the INDF register
actually accesses the register pointed to by the File
Select Register, FSR. Reading the INDF register itself,
indirectly (FSR = ’0’), will read 00h. Writing to the INDF
register indirectly, results in a no operation. The FSR
register contains a 12-bit address, which is shown in
Figure 4-10.
The INDFn register is not a physical register. Address-
ing INDFn actually addresses the register whose
address is contained in the FSRn register (FSRn is a
pointer). This is indirect addressing.
Example 4-4 shows a simple use of indirect addressing
to clear the RAM in Bank1 (locations 100h-1FFh) in a
minimum number of instructions.
EXAMPLE 4-4:
There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12-bit wide. To store the 12-bits of
addressing information, two 8-bit registers are
required. These indirect addressing registers are:
1.
2.
3.
In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect address-
ing, with the value in the corresponding FSR register
being the address of the data.
If an instruction writes a value to INDF0, the value will
be written to the address pointed to by FSR0H:FSR0L.
A read from INDF1 reads the data from the address
pointed to by FSR1H:FSR1L. INDFn can be used in
code anywhere an operand can be used.
DS39026C-page 50
NEXT
CONTINUE
FSR0: composed of FSR0H:FSR0L
FSR1: composed of FSR1H:FSR1L
FSR2: composed of FSR2H:FSR2L
LFSR
CLRF
BTFSS FSR0H, 1
GOTO
Indirect Addressing, INDF and
FSR Registers
FSR0, 0x100
POSTINC0
NEXT
HOW TO CLEAR RAM
(BANK1) USING INDIRECT
ADDRESSING
;
; Clear INDF register
; & inc pointer
; All done w/ Bank1?
; NO, clear next
; YES, continue
If INDF0, INDF1 or INDF2 are read indirectly via an
FSR, all ’0’s are read (zero bit is set). Similarly, if
INDF0, INDF1 or INDF2 are written to indirectly, the
operation will be equivalent to a NOP instruction and the
STATUS bits are not affected.
4.12.1
Each FSR register has an INDF register associated
with it, plus four additional register addresses. Perform-
ing an operation on one of these five registers deter-
mines how the FSR will be modified during indirect
addressing.
When data access is done to one of the five INDFn
locations, the address selected will configure the FSRn
register to:
• Do nothing to FSRn after an indirect access (no
• Auto-decrement FSRn after an indirect access
• Auto-increment FSRn after an indirect access
• Auto-increment FSRn before an indirect access
• Use the value in the WREG register as an offset
When using the auto-increment or auto-decrement fea-
tures, the effect on the FSR is not reflected in the
STATUS register. For example, if the indirect address
causes the FSR to equal '0', the Z bit will not be set.
Incrementing or decrementing an FSR affects all 12
bits. That is, when FSRnL overflows from an increment,
FSRnH will be incremented automatically.
Adding these features allows the FSRn to be used as a
stack pointer, in addition to its uses for table operations
in data memory.
Each FSR has an address associated with it that per-
forms an indexed indirect access. When a data access
to this INDFn location (PLUSWn) occurs, the FSRn is
configured to add the signed value in the WREG regis-
ter and the value in FSR to form the address before an
indirect access. The FSR value is not changed.
If an FSR register contains a value that points to one of
the INDFn, an indirect read will read 00h (zero bit is
set), while an indirect write will be equivalent to a NOP
(STATUS bits are not affected).
change) - INDFn
(post-decrement) - POSTDECn
(post-increment) - POSTINCn
(pre-increment) - PREINCn
to FSRn. Do not modify the value of the WREG or
the FSRn register after an indirect access (no
change) - PLUSWn
INDIRECT ADDRESSING
OPERATION
2001 Microchip Technology Inc.