AT89C51CC03C-7CTIM Atmel, AT89C51CC03C-7CTIM Datasheet - Page 133
AT89C51CC03C-7CTIM
Manufacturer Part Number
AT89C51CC03C-7CTIM
Description
IC 8051 MCU FLASH 64K 64BGA
Manufacturer
Atmel
Series
AT89C CANr
Datasheets
1.AT89C51CC03C-S3RIM.pdf
(198 pages)
2.AT89C51CC03C-S3RIM.pdf
(32 pages)
3.AT89C51CC03C-S3RIM.pdf
(27 pages)
4.AT89C51CC03C-S3RIM.pdf
(184 pages)
Specifications of AT89C51CC03C-7CTIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
AT89C51CC03C7CTIM
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Serial Peripheral Status Register
and Control (SPSCR)
4182E–CAN–05/04
Reset Value = 0001 0100b
Not bit addressable
The Serial Peripheral Status Register contains flags to signal the following conditions:
•
•
•
Table 93. SPSCR Register
SPSCR - Serial Peripheral Status and Control register (0D5H)
Bit Number
Number
SPIF
Data transfer complete
Write collision
Inconsistent logic level on SS pin (mode fault error)
Bit
7
7
6
5
3
2
1
0
Mnemonic Description
SPIF
OVR
Bit
Bit Mnemonic
6
-
-
CPOL
CPHA
SPR1
SPR0
Serial Peripheral Data Transfer Flag
Cleared by hardware to indicate data transfer is in progress or has been
approved by a clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
This bit is cleared when reading or writing SPDATA after reading SPSCR.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Overrun Error Flag
- Set by hardware when a byte is received whereas SPIF is set (the previous
received data is not overwritten).
- Cleared by hardware when reading SPSCR
OVR
5
Description
Clock Polarity
Cleared to have the SCK set to ’0’ in idle state.
Set to have the SCK set to ’1’ in idle state.
Clock Phase
Cleared to have the data sampled when the SCK leaves the idle
state (see CPOL).
Set to have the data sampled when the SCK returns to idle state (see
CPOL).
SPR2
0
0
0
0
1
1
1
1
MODF
4
SPR1
0
0
1
1
0
0
1
1
SPR0 Serial Peripheral Rate
SPTE
0
1
0
1
0
1
0
1
3
Invalid
F
F
F
F
F
F
Invalid
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
UARTM
AT89C51CC03
2
/4
/8
/16
/32
/64
/128
SPTEIE
1
MODFIE
0
133
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