PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 12

• Manufacturer Part Number: PIC32MX460F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX3XX/4XX
31. Module: USB
32. Module: USB
33. Module: Prefetch Cache
DS80440D-page 12
The D+ and D– pins are not 5V tolerant. During
normal operation these pins are not subject to 5V.
The 5V tolerance specification is intended to
prevent device damage in an abnormal operation
mode such as connecting a shorted USB cable to
the device.
Work around
Affected Silicon Revisions
The single-ended comparator is detecting SE0
transitions at a higher voltage than indicated in the
USB specification. This is a compliance issue
relating to items ST2 and ST3 in the Peripheral
Silicon checklist, which may result in reduced
noise immunity.
Work around
None.
Affected Silicon Revisions
If the Predictive Prefetch Cache Enable bits
(PREFEN<1:0>) in the CHECON register are non-
zero, improper processor behavior may occur
during a rare boundary condition. This condition
occurs only when predictive prefetch is enabled,
and can occur in both cacheable and non-
cacheable memory areas. The prefetch buffer can
be
instructions causing invalid instruction execution.
This may cause an invalid instruction fault, or
execution of a wrong instruction.
Work around
Make sure that the PREFEN field in CHECON is
programmed to ‘00’. The cache is still used,
although predictive prefetching will be disabled.
Affected Silicon Revisions
Do not subject D+ or D– to 5V.
B2
B2
B2
X
X
X
overwritten
B3
B3
B3
X
X
B4
B4
B4
by
B6
B6
B6
the
“next”
16-bytes
of
34. Module: Flash Program Memory
35. Module: ADC
36. Module: Timers
NVM registers must not be written immediately
after a programming operation is complete. When
a NVM operation completes, the NVMWR bit
(NVMCON<15>) switches states from ‘1’ to ‘0’,
indicating that another NVM operation may be
started. However, there is a period of two internal
FRC clocks after this transition where a write to
NVMCON may not work correctly. Since the
internal FRC clock is 8 MHz, and the system clock
may be much faster, care must be taken to ensure
that the correct delay is met.
Work around
Wait at least 500 ns after seeing a ‘0’ in
NVMCON<15> before writing to any NVM
registers.
Affected Silicon Revisions
When the ADC is in operation, the current channel
is shorted to V
(12 T
impedance sources is that they may not have time
to recover between conversions. The impact on
low-impedance sources is a high current draw,
which may damage either the source or the
device.
Work around
Place a 5k resistor between the device and any
external capacitance on the board to limit current
draw.
Affected Silicon Revisions
Writes to the timer registers PRx and TIMERx
through the Set/Clear/Invert registers corrupts the
data written.
Work around
Do not write to the affected Set/Clear/Invert regis-
ters. Use software read-modify-write sequences to
change individual bits or write directly to the PRx
and TIMERx registers.
Affected Silicon Revisions
B2
B2
B2
X
X
X
AD
) after sampling. The impact on high-
B3
B3
B3
X
B4
B4
B4
X
REF
© 2010 Microchip Technology Inc.
during the conversion period
B6
B6
B6
X