PIC18LF458-I/PT Microchip Technology, PIC18LF458-I/PT Datasheet - Page 289

IC MCU CAN FLASH 16K LP 44-TQFP

PIC18LF458-I/PT

Manufacturer Part Number
PIC18LF458-I/PT
Description
IC MCU CAN FLASH 16K LP 44-TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF458-I/PT

Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
PIC18
No. Of I/o's
33
Eeprom Memory Size
256Byte
Ram Memory Size
1.5KB
Cpu Speed
40MHz
No. Of Timers
4
Package
44TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
33
Interface Type
CAN/I2C/SPI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF458-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18LF458-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
25.2
ADDLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2006 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Instruction Set
W
W
Q1
=
=
ADD Literal to W
[ label ] ADDLW
0
(W) + k
N, OV, C, DC, Z
The contents of W are added to the 8-bit
literal ‘k’ and the result is placed in W.
1
1
0x10
0x25
literal ‘k’
ADDLW
0000
k
Read
Q2
255
W
0x15
1111
Process
Data
Q3
k
kkkk
Write to W
Q4
kkkk
ADDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
REG
W
REG
Q1
=
=
=
=
register ‘f’
ADD W to f
[ label ] ADDWF
0
d
a
(W) + (f)
N, OV, C, DC, Z
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access Bank
will be selected. If ‘a’ is ‘1’, the BSR is
used.
1
1
ADDWF
Read
0010
Q2
f
[0,1]
[0,1]
0x17
0xC2
0xD9
0xC2
255
PIC18FXX8
dest
01da
REG, W
Process
Data
Q3
DS41159E-page 287
f [,d [,a]]
ffff
destination
Write to
Q4
ffff

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