PIC18LF458-I/PT Microchip Technology, PIC18LF458-I/PT Datasheet - Page 82

• Manufacturer Part Number: PIC18LF458-I/PT
• Description: IC MCU CAN FLASH 16K LP 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF458-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 33
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 1.5KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 33
• Interface Type: CAN/I2C/SPI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 8-2:
DS41159E-page 80
PIC18FXX8
bit 7
bit 6
bit 5
bit 4-3
bit 2
bit 1
bit 0
INTCON2: INTERRUPT CONTROL REGISTER 2
bit 7
RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
Unimplemented: Read as ‘0’
TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
Unimplemented: Read as ‘0’
RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit
-n = Value at POR
Note:
R/W-1
RBPU
Interrupt flag bits are set when an interrupt condition occurs regardless of the state
of its corresponding enable bit or the global interrupt enable bit. User software
should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt. This feature allows software polling.
INTEDG0 INTEDG1
R/W-1
R/W-1
W = Writable bit
‘1’ = Bit is set
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
TMR0IP
R/W-1
© 2006 Microchip Technology Inc.
x = Bit is unknown
U-0
—
R/W-1
RBIP
bit 0