ATXMEGA192A3-MH Atmel, ATXMEGA192A3-MH Datasheet - Page 48

• Manufacturer Part Number: ATXMEGA192A3-MH
• Description: MCU AVR 192K FLASH 1.8V 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA192A3-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 192KB (96K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA192x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 2 Channel
• On-chip Dac: 2 bit, 1 Channel
• Package: 64QFN EP
• Device Core: AVR
• Family Name: XMEGA
• Maximum Speed: 32 MHz
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA192A3-MU; ATXMEGA192A3-MU

29. Program and Debug Interfaces
29.1
29.2
29.3
29.3.1
29.3.2
8068T–AVR–12/10
Features
Overview
IEEE 1149.1 (JTAG) Boundary-scan
Boundary-scan Order
Boundary-scan Description Language Files
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The programming and debug facilities are accessed through the JTAG and PDI physical inter-
faces. The PDI physical interface uses one dedicated pin together with the Reset pin, and no
general purpose pins are used. JTAG uses four general purpose pins on PORTB.
The PDI is an Atmel proprietary protocol for communication between the microcontroller and
Atmel’s or third party development tools.
The JTAG physical layer handles the basic low-level serial communication over four I/O lines
named TMS, TCK, TDI, and TDO. It complies to the IEEE Std. 1149.1 for test access port and
boundary scan.
Table 30-8 on page 53
chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned
out. The scan order follows the pin-out order. Bit 4, 5, 6 and 7 of Port B is not in the scan chain,
since these pins constitute the TAP pins when the JTAG is enabled.
Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in
a standard format used by automated test-generation software. The order and function of bits in
the Boundary-scan Data Register are included in this description. BSDL files are available for
ATxmega256/192/128/64A3 devices.
See
PDI - Program and Debug Interface (Atmel proprietary 2-pin interface)
JTAG Interface (IEEE std. 1149.1 compliant)
Boundary-scan capabilities according to the IEEE Std. 1149.1 (JTAG)
Access to the OCD system
Programming of Flash, EEPROM, Fuses and Lock Bits
Table 30-8 on page 53
shows the Scan order between TDI and TDO when the Boundary-scan
for ATxmega256/192/128/64A3 Boundary Scan Order.
XMEGA A3
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