PIC16LC74A-04I/L Microchip Technology, PIC16LC74A-04I/L Datasheet - Page 33

• Manufacturer Part Number: PIC16LC74A-04I/L
• Description: IC MCU OTP 4KX14 A/D PWM 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC74A-04I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Core: PIC
• Processor Series: PIC16LC
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 192 B
• Data Rom Size: 192 B
• On-chip Adc: Yes
• Number Of Programmable I/os: 33
• Number Of Timers: 3
• Mounting Style: SMD/SMT
• A/d Bit Size: 8 bit
• A/d Channels Available: 8
• Height: 3.87 mm
• Interface Type: I2C, SPI, USART
• Length: 16.59 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2.5 V
• Width: 16.59 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.2.2.4
This register contains the individual enable bits for the
peripheral interrupts.
FIGURE 4-10: PIE1 REGISTER PIC16C72 (ADDRESS 8Ch)
1997 Microchip Technology Inc.
bit7
bit 7:
bit 6:
bit 5-4: Unimplemented: Read as '0'
bit 3:
bit 2:
bit 1:
bit 0:
U-0
—
PIE1 REGISTER
Applicable Devices
72 73 73A 74 74A 76 77
Unimplemented: Read as '0'
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
R/W-0
ADIE
U-0
—
U-0
—
SSPIE
R/W-0
CCP1IE
R/W-0
TMR2IE
R/W-0
Note:
TMR1IE
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
R/W-0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
read as ‘0’
PIC16C7X
DS30390E-page 33