ATMEGA640V-8CU Atmel, ATMEGA640V-8CU Datasheet - Page 163
![IC MCU AVR 64K FLASH 100-CBGA](/photos/6/89/68968/313-100-cbga_sml.jpg)
ATMEGA640V-8CU
Manufacturer Part Number
ATMEGA640V-8CU
Description
IC MCU AVR 64K FLASH 100-CBGA
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA640V-8CU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
86
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
86
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK503 - STARTER KIT AVR EXP MODULE 100P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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16.11.15 TCNT4H and TCNT4L –Timer/Counter 4
16.11.16 TCNT5H and TCNT5L –Timer/Counter 5
16.11.17 OCR1AH and OCR1AL – Output Compare Register 1 A
16.11.18 OCR1BH and OCR1BL – Output Compare Register 1 B
16.11.19 OCR1CH and OCR1CL – Output Compare Register 1 C
2549M–AVR–09/10
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers.
Registers” on page 138.
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a com-
pare match between TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock
for all compare units.
Bit
(0xA5)
(0xA4)
Read/Write
Initial Value
Bit
(0x125)
(0x124)
Read/Write
Initial Value
Bit
(0x89)
(0x88)
Read/Write
Initial Value
Bit
(0x8B)
(0x8A)
Read/Write
Initial Value
Bit
(0x8D)
(0x8C)
Read/Write
Initial Value
R/W
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
7
0
R/W
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
6
0
ATmega640/1280/1281/2560/2561
R/W
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
5
0
R/W
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
4
0
OCR1A[15:8]
OCR1B[15:8]
OCR1C[15:8]
TCNT4[15:8]
TCNT5[15:8]
OCR1A[7:0]
OCR1B[7:0]
OCR1C[7:0]
TCNT4[7:0]
TCNT5[7:0]
R/W
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
3
0
R/W
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
2
0
R/W
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
1
0
See “Accessing 16-bit
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
OCR1AH
OCR1BH
OCR1CH
OCR1AL
OCR1BL
OCR1CL
TCNT4H
TCNT4L
TCNT5H
TCNT5L
163
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