ATMEGA640V-8CU Atmel, ATMEGA640V-8CU Datasheet - Page 332
![IC MCU AVR 64K FLASH 100-CBGA](/photos/6/89/68968/313-100-cbga_sml.jpg)
ATMEGA640V-8CU
Manufacturer Part Number
ATMEGA640V-8CU
Description
IC MCU AVR 64K FLASH 100-CBGA
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA640V-8CU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
86
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
86
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK503 - STARTER KIT AVR EXP MODULE 100P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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28.7
28.7.1
2549M–AVR–09/10
Register Description
SPMCSR – Store Program Memory Control and Status Register
Table 28-14. Read-While-Write Limit, ATmega2560/2561
Note:
Table 28-15. Explanation of different variables used in
Notes:
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Boot Loader operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN
bit in the SPMCSR Register is cleared.
Bit
0x37 (0x57)
Read/Write
Initial Value
Section
Read-While-Write section (RWW)
No Read-While-Write section (NRWW)
Variable
PCMSB
PAGEMSB
ZPCMSB
ZPAGEMSB
PCPAGE
PCWORD
1. For details about these two section, see
1. Z0: should be zero for all SPM commands, byte select for the (E)LPM instruction.
2. See
3. The Z-register is only 16 bits wide. Bit 16 is located in the RAMPZ register in the I/O map.
(1)
318
Z-pointer during Self-Programming.
ping to the Z-pointer, ATmega2560/2561
SPMIE
and
“Addressing the Flash During Self-Programming” on page 322
R/W
7
0
PC[16:7]
PC[6:0]
“RWW – Read-While-Write Section” on page
16
6
RWWSB
R
6
0
Corresponding
Z17:Z16
Z-value
ATmega640/1280/1281/2560/2561
Z17
SIGRD
R/W
Z7:Z1
5
0
Z7
(3)
:Z8
(2)
(3)
RWWSRE
R/W
4
0
Description
Most significant bit in the Program Counter. (The
Program Counter is 17 bits PC[16:0]).
Most significant bit which is used to address the
words within one page (128 words in a page
requires seven bits PC [6:0]).
Bit in Z-pointer that is mapped to PCMSB. Because
Z0 is not used, the ZPCMSB equals PCMSB + 1.
Bit in Z-pointer that is mapped to PCMSB. Because
Z0 is not used, the ZPAGEMSB equals PAGEMSB +
1.
Program Counter page address: Page select, for
Page Erase and Page Write.
Program Counter word address: Word select, for
filling temporary buffer (must be zero during Page
Write operation).
“NRWW – No Read-While-Write Section” on page
BLBSET
R/W
3
0
Figure 28-3 on page 322
Pages
992
32
(1)
318.
PGWRT
R/W
2
0
Address
0x00000 - 0x1EFFF
0x1F000 - 0x1FFFF
PGERS
for details about the use of
R/W
1
0
SPMEN
R/W
and the map-
0
0
SPMCSR
332
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