PIC16LC65A-04I/L Microchip Technology, PIC16LC65A-04I/L Datasheet - Page 44
PIC16LC65A-04I/L
Manufacturer Part Number
PIC16LC65A-04I/L
Description
IC MCU OTP 4KX14 PWM 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC65A-04I/L
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Package
44PLCC
Device Core
PIC
Family Name
PIC16
Maximum Speed
4 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
33
Interface Type
I2C/SPI/USART
Number Of Timers
3
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LC65A-04I/L
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC16C63A/65B/73B/74B
7.1
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is F
(T1CON<2>) has no effect since the internal clock is
always in sync.
FIGURE 7-1:
DS30605C-page 44
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
Timer1 Operation in Timer Mode
OSC
2: For the PIC16C65B/73B/74B, the Schmitt Trigger is not implemented in External Clock mode.
/4. The synchronize control bit T1SYNC
Set Flag bit
TMR1IF on
Overflow
TIMER1 BLOCK DIAGRAM
(2)
TMR1H
T1OSC
TMR1
TMR1L
Oscillator
Enable
T1OSCEN
(1)
(2)
Internal
Clock
F
OSC
/4
TMR1ON
7.2
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2, when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when
bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple counter.
In this configuration during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut-off. The
prescaler, however, will continue to increment.
On/Off
TMR1CS
1
0
Timer1 Operation in Synchronized
Counter Mode
T1CKPS1:T1CKPS0
T1SYNC
Prescaler
1, 2, 4, 8
0
1
2
2000 Microchip Technology Inc.
Synchronized
Clock Input
Synchronize
SLEEP Input
det
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