PIC18F8628-I/PT Microchip Technology, PIC18F8628-I/PT Datasheet - Page 47

• Manufacturer Part Number: PIC18F8628-I/PT
• Description: IC PIC MCU FLASH 48KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8628-I/PT

• Core Size: 8-Bit
• Program Memory Size: 96KB (48K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 70
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 1024Byte
• Cpu Speed: 40MHz
• No.: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIGURE 4-4:
TABLE 4-2:
© 2009 Microchip Technology Inc.
130
131
132
135
137
Note 1:
Param
No.
Note 1:
A/D CLK
A/D DATA
SAMPLE
2:
3:
4:
ADRES
BSF ADCON0, GO
T
T
T
T
T
Symbol
ADIF
AD
CNV
ACQ
SWC
DIS
2:
GO
Q4
The time of the A/D clock period is dependent on the device frequency and the T
ADRES registers may be read on the following T
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
On the following cycle of the device clock.
(1)
If the A/D clock source is selected as RC, a time of T
to be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
132
A/D CONVERSION REQUIREMENTS
A/D Clock Period
Conversion Time
(not including acquisition time)
Acquisition Time
Switching Time from Convert → Sample
Discharge Time
A/D CONVERSION TIMING
(Note 2)
Characteristic
DD
11
(3)
to V
10
SS
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
or V
OLD_DATA
9
SS
(2)
to V
. . .
SAMPLING STOPPED
CY
DD
is added before the A/D clock starts. This allows the SLEEP instruction
). The source impedance (R
CY
. . .
130
131
cycle.
Min
PIC18F8723 FAMILY
0.8
1.4
1.4
0.2
13
—
—
—
3
(Note 4)
12.5
25.0
Max
14
—
—
1
3
2
(1)
(1)
Units
1
T
μs
μs
μs
μs
μs
μs
AD
S
) on the input channels is 50Ω.
T
V
T
A/D RC mode
V
0
OSC
OSC
DD
DD
AD
= 3.0V;
= 3.0V; A/D RC mode
based, V
based, V
clock divider.
NEW_DATA
DONE
Conditions
T
DS39894B-page 47
CY
REF
REF
≥ 3.0V
full range