DSPIC30F6014A-30I/PF Microchip Technology, DSPIC30F6014A-30I/PF Datasheet - Page 92

• Manufacturer Part Number: DSPIC30F6014A-30I/PF
• Description: IC DSPIC MCU/DSP 144K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6014A-30I/PF

• Program Memory Type: FLASH
• Program Memory Size: 144KB (48K x 24)
• Package / Case: 80-TQFP, 80-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 68
• Data Ram Size: 8 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300024 - KIT DEMO DSPICDEM 1.1DM300019 - BOARD DEMO DSPICDEM 80L STARTERDM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC164314 - MODULE SKT FOR PM3 80PFAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC30F6011A/6012A/6013A/6014A
14.2
The module supports a basic framed SPI protocol in
Master or Slave mode. The control bit FRMEN enables
framed SPI support and causes the SSx pin to perform
the frame synchronization pulse (FSYNC) function.
The control bit SPIFSD determines whether the SSx
FIGURE 14-1:
FIGURE 14-2:
DS70143E-page 92
Note: x = 1 or 2, y = 1 or 2.
Framed SPI Support
Note: x = 1 or 2.
SDOx
SCKx
SDIx
SSx
MSb
PROCESSOR 1
SS and FSYNC
SPI BLOCK DIAGRAM
SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
SPI Master
Shift Register
Control
(SPIxBUF)
Receive
(SPIxSR)
SPIxBUF
Read
bit 0
LSb
SPIxSR
Control
Clock
SDOx
SCKx
SDIx
Clock
Shift
SPIxBUF
Write
Transmit
Serial Clock
Data Bus
Internal
Select
Edge
pin is an input or an output (i.e., whether the module
receives or generates the frame synchronization
pulse). The frame pulse is an active-high pulse for a
single SPI clock cycle. When frame synchronization is
enabled, the data transmission starts only on the
subsequent transmit edge of the SPI clock.
SDOy
SCKy
SDIy
Enable Master Clock
Secondary
MSb
Prescaler
1:1 – 1:8
Serial Input Buffer
Shift Register
PROCESSOR 2
(SPIyBUF)
(SPIySR)
SPI Slave
© 2011 Microchip Technology Inc.
1, 4, 16, 64
Prescaler
Primary
LSb
F
CY