PIC18C858-I/L Microchip Technology, PIC18C858-I/L Datasheet - Page 48

• Manufacturer Part Number: PIC18C858-I/L
• Description: IC PIC MCU OTP 16KX16 84PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C858-I/L

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Number Of I /o: 68
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Controller Family/series: PIC18
• No. Of I/o's: 68
• Ram Memory Size: 1.5KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: 3-Wire, I2C, SPI, USART, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 68
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163007, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C858I/L

PIC18CXX8
4.9
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. Figure 4-4
shows the data memory organization for the
PIC18CXX8 devices.
The data memory map is divided into as many as 16
banks that contain 256 bytes each. The lower 4 bits of
the Bank Select Register (BSR<3:0>) select which
bank will be accessed. The upper 4 bits for the BSR are
not implemented.
The data memory contains Special Function Registers
(SFR) and General Purpose Registers (GPR). The
SFR’s are used for control and status of the controller
and peripheral functions, while GPR’s are used for data
storage and scratch pad operations in the user’s appli-
cation. The SFR’s start at the last location of Bank 15
(0xFFF) and grow downwards. GPR’s start at the first
location of Bank 0 and grow upwards. Any read of an
unimplemented location will read as ’0’s.
The entire data memory may be accessed directly or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of
the File Select Register (FSR). Each FSR holds a
12-bit address value that can be used to access any
location in the Data Memory map without banking.
The instruction set and architecture allow operations
across all banks. This may be accomplished by indirect
addressing or by the use of the MOVFF instruction. The
MOVFF instruction is a two word/two cycle instruction
that moves a value from one register to another.
To ensure that commonly used registers (SFR’s and
select GPR’s) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment of
Bank 15 comprise the Access RAM. Section 4.10 pro-
vides a detailed description of the Access RAM.
DS30475A-page 48
Data Memory Organization
Advanced Information
4.9.1
The register file can be accessed either directly or indi-
rectly. Indirect addressing operates through the File
Select Registers (FSR). The operation of indirect
addressing is shown in Section 4.12.
Enhanced MCU devices may have banked memory in
the GPR area. GPR’s are not initialized by a Power-on
Reset and are unchanged on all other RESETS.
Data RAM is available for use as GPR registers by all
instructions. Bank 15 (0xF00 to 0xFFF) contains
SFR’s. All other banks of data memory contain GPR
registers starting with bank 0.
4.9.2
The Special Function Registers (SFR’s) are registers
used by the CPU and Peripheral Modules for control-
ling the desired operation of the device. These regis-
ters are implemented as static RAM. A list of these
registers is given in Table 4-2.
The SFR’s can be classified into two sets: those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature.
The SFR’s are typically distributed among the peripher-
als whose functions they control.
The unused SFR locations will be unimplemented and
read as '0's. See Table 4-2 for addresses for the SFR’s.
GENERAL PURPOSE REGISTER FILE
SPECIAL FUNCTION REGISTERS
 2000 Microchip Technology Inc.