PIC18C858-I/L Microchip Technology, PIC18C858-I/L Datasheet - Page 3

• Manufacturer Part Number: PIC18C858-I/L
• Description: IC PIC MCU OTP 16KX16 84PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C858-I/L

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Number Of I /o: 68
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Controller Family/series: PIC18
• No. Of I/o's: 68
• Ram Memory Size: 1.5KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: 3-Wire, I2C, SPI, USART, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 68
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163007, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C858I/L

8. Module: WDT
9. Module: MSSP (I
10. Module: I/O (Parallel Slave Port)
 2003 Microchip Technology Inc.
When the device is configured for either EC or RC
oscillator modes, with the Power-up Timer
enabled, bit TO of the RCON register (RCON<3>)
may default to ‘0’, even though no WDT time-out
has occurred.
The TO bit functions normally in all other configu-
rations.
Work around
1. Use bit TO in conjunction with bit POR
2. Use the latest silicon revision when it becomes
The BF Status bit (SSPSTAT<0>) may be reset by
certain literal operations, even if the buffer has not
been read. This will occur when both of the
following conditions are met:
•
•
Work around
1. Before performing any literal operation with an
2. Use the latest silicon revision when it becomes
The Input Buffer Status bit of the PSPCON register
(PSPCON<7>) may be inadvertently cleared,
even when the PORTD input buffer has not been
read. This will occur only when the following two
conditions occur simultaneously:
•
•
(RCON<1>), to determine if a RESET
condition has occurred.
available.
argument of 0C9h, verify that the contents of
the BSR are not 0Fh.
available.
The four Least Significant bits of the
BSR register are equal to 0Fh
(BSR<3:0> = 1111), and
Any instruction that contains 83h in its
8 Least Significant bits (i.e., register file
addresses, literal data, address offsets,
etc.) is executed.
The literal contents of the Bank Select
Register (BSR) are 0Fh, and
A literal operation with an argument of 0C9h
is performed.
2
C
TM
Master Mode)
11. Module: Interrupts
Work around
All work arounds will involve setting the contents of
BSR<3:0> to some value other than 0Fh. In addition
to those proposed below, other solutions may exist.
1. When developing or modifying code, keep
2. If accessing a part of Bank 15 is required and
3. If pointing the BSR to Bank 15 is unavoidable,
High-priority interrupts may become improperly
enabled, while low priority interrupts become
improperly disabled at the same time. This may
occur when low priority interrupts are in an
enabled state and the following conditions occur
simultaneously:
•
•
Work around
1. Always disable low priority interrupts before
2. Use the latest silicon revision when it becomes
these guidelines in mind:
•
•
•
the use of Access Banking is not possible,
consider using indirect addressing.
review the absolute file listing. Verify that no
instructions contains 83h in the 8 Least Signif-
icant bits while the BSR points to Bank 15
(BSR = 0Fh).
High priority interrupts are being changed
from an enabled to a disabled state; and
One or more low priority interrupts occur.
disabling high priority interrupts. Re-enable
the low priority interrupts afterwards, if neces-
sary.
available.
Assign 12-bit addresses to all variables.
This allows the assembler to know when
Access Banking can be used.
Do not set the BSR to point to Bank 15
(BSR = 0Fh).
Allow the assembler to manipulate the
Access bit present in most instructions.
Accessing the SFRs in Bank 15 will be
done through the Access Bank. Con-
tinue to use the BSR to select Banks 1
through 5 and the upper half of Bank 0.
PIC18C658/858
DS80084M-page 3