PIC16C771/JW Microchip Technology, PIC16C771/JW Datasheet - Page 101

• Manufacturer Part Number: PIC16C771/JW
• Description: IC MCU EPROM4KX14 A/D PWM 20CDIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C771/JW

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: EPROM, UV
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-CDIP (0.300", 7.62mm) Window
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGDVA16XP200 - ADAPTER ICE 20DIP/SOIC/SSOPAC164028 - MODULE SKT PROMATEII 20SOIC/DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Q1066306

9.2.18
For Standard mode I
resistors R
lowing parameters
• Supply voltage
• Bus capacitance
• Number of connected devices (input current +
The supply voltage limits the minimum value of resistor
R
at V
FIGURE 9-31:
TABLE 9-3:
Legend:
p
10Bh,18Bh
2002 Microchip Technology Inc.
leakage current).
Note: I
0Bh, 8Bh,
Address
due to the specified minimum sink current of 3 mA
OL
0Ch
8Ch
0Dh
8Dh
13h
14h
91h
94h
93h
max = 0.4V for the specified output stages. For
connected.
2
C devices with input levels related to V
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the MSSP in I
p
CONNECTION CONSIDERATIONS
FOR I
and R
SSPCON2
SSPSTAT
SSPCON
SSPBUF
SSPADD
INTCON
Name
PIR1
PIE1
PIR2
PIE2
REGISTERS ASSOCIATED WITH I
2
s
C BUS
in Figure 9-31 depends on the fol-
2
SAMPLE DEVICE CONFIGURATION FOR I
C bus devices, the values of
WCOL
LVDIE
GCEN
LVDIF
Bit 7
SMP
GIE
—
—
SDA
SCL
ACKSTAT
SSPOV
PEIE
ADIF
ADIE
Bit 6
CKE
—
—
Synchronous Serial Port Receive Buffer/Transmit Register
Rp
Synchronous Serial Port (I
SSPEN
ACKDT
DD
Bit 5
T0IE
Advance Information
D/A
—
—
—
—
Rp
must have one common supply line to which the pull-up resistor is also
ACKEN
Bit 4
INTE
CKP
—
—
—
—
P
Rs
V
2
DD
2
DEVICE
SSPM3
C Mode) Address Register
C OPERATION
SSPIF
SSPIE
BCLIE
BCLIF
RCEN
RBIE
Bit 3
Rs
+ 10%
S
example, with a supply voltage of V
V
1.7 k
The desired noise margin of 0.1V
limits the maximum value of R
optional and used to improve ESD susceptibility.
The bus capacitance is the total capacitance of wire,
connections, and pins. This capacitance limits the max-
imum value of R
(Figure 9-31).
The SMP bit is the slew rate control enabled bit. This bit
is in the SSPSTAT register, and controls the slew rate
of the I/O pins when in I
OL
PIC16C717/770/771
CCP1IE
max = 0.4V at 3 mA, R
CCP1IF
SSPM2
Bit 2
T0IF
PEN
R/W
—
—
V
2
DD
C BUS
as a function of R
TMR2IF
TMR2IE
SSPM1
RSEN
INTF
Bit 1
UA
—
—
p
due to the specified rise time
TMR1IE
TMR1IF
CCP2IF
CCP2IE
SSPM0
2
RBIF
Bit 0
C mode (master or slave).
SEN
BF
Cb=10 pF to 400 pF
2
p
p min
C mode.
is shown in Figure 9-31.
s
0000 000x
-0-- 0000
-0-- 0000
0--- 0--0
0--- 0--0
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
POR, BOR
. Series resistors are
DD
= (5.5-0.4)/0.003 =
DD
DS41120B-page 99
for the low level
= 5V+10% and
MCLR, WDT
0000 000u
-0-- 0000
-0-- 0000
0--- 0--0
0--- 0--0
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000