PIC16C771/JW Microchip Technology, PIC16C771/JW Datasheet - Page 20

• Manufacturer Part Number: PIC16C771/JW
• Description: IC MCU EPROM4KX14 A/D PWM 20CDIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C771/JW

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: EPROM, UV
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-CDIP (0.300", 7.62mm) Window
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGDVA16XP200 - ADAPTER ICE 20DIP/SOIC/SSOPAC164028 - MODULE SKT PROMATEII 20SOIC/DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Q1066306

PIC16C717/770/771
2.2.2.5
This register contains the individual flag bits for the
peripheral interrupts.
REGISTER 2-5:
DS41120B-page 18
bit 7
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
PIR1 REGISTER
PERIPHERAL INTERRUPT REGISTER 1 (PIR1: 0Ch)
bit 7
Unimplemented: Read as ‘0’.
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
Unimplemented: Read as ’0’
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1 = The SSP interrupt condition has occurred, and must be cleared in software before returning
0 = No SSP interrupt condition has occurred.
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit
- n = Value at POR
U-0
from the Interrupt Service Routine. The conditions that will set this bit are:
SPI
I
I
—
2
2
C Slave / Master
C Master
A transmission/reception has taken place.
A transmission/reception has taken place.
The initiated START condition was completed by the SSP module.
The initiated STOP condition was completed by the SSP module.
The initiated Restart condition was completed by the SSP module.
The initiated Acknowledge condition was completed by the SSP module.
A START condition occurred while the SSP module was IDLE (Multi-master system).
A STOP condition occurred while the SSP module was IDLE (Multi-master system).
R/W-0
ADIF
U-0
—
W = Writable bit
’1’ = Bit is set
U-0
—
Note:
SSPIF
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
CCP1IF
R/W-0
2002 Microchip Technology Inc.
x = Bit is unknown
TMR2IF
R/W-0
TMR1IF
R/W-0
bit 0