PIC18F8720-I/PT Microchip Technology, PIC18F8720-I/PT Datasheet - Page 38

• Manufacturer Part Number: PIC18F8720-I/PT
• Description: IC MCU FLASH 64KX16 EE 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8720-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Eeprom Size: 1K x 8
• Ram Size: 3.75K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.75 KB
• Interface Type: I2C/SPI/USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 68
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183032, DM183022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18FXX20
6.0
DS39583C-page 38
Standard Operating Conditions
Operating Temperature: 25C is recommended
D110
D110A
D111
D112
D113
D031
D041
D080
D090
D012
P1
P2
P2A
P2B
P3
P4
P5
P5A
P6
P9
P10
P11
P11A
P12
P13
P14
P15
Param
Note 1: Do not allow excess time when transitioning MCLR between V
No.
AC/DC CHARACTERISTICS
TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE
V
V
V
I
I
V
V
V
V
C
T
Tsclk
TsclkL
TsclkH
Tset1
Thld1
Tdly1
Tdly1a
Tdly2
Tdly5
Tdly6
Tdly7
Tdrwt
Thld2
Tset2
Tvalid
Tset3
PP
DDP
executions to occur. The maximum transition time is:
1 T
+ 2 ms (for HS/PLL mode only) + 1.5 s (for EC mode only)
where T
For specific values, refer to the Electrical Characteristics section of the Device Data Sheet for the particular device.
R
Sym
IHH
IH
DD
IL
IH
OL
OH
IO
L
CY
+ T
CY
High Voltage Programming Voltage on
MCLR/V
Low Voltage Programming Voltage on
MCLR/V
Supply Voltage During Programming
Programming Current on MCLR/V
Supply Current During Programming
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Capacitive Loading on I/O pin (SDATA)
MCLR/V
Program/Verify mode
Serial Clock (SCLK) Period
Serial Clock (SCLK) Low Time
Serial Clock (SCLK) High Time
Input Data Setup Time to Serial Clock 
Input Data Hold Time from SCLK
Delay between 4-bit Command and
Command Operand
Delay between 4-bit Command
Operand and next 4-bit Command
Delay between Last SCLK  of
Command Byte to First SCLK  of Read
of Data Word
SCLK High Time
SCLK Low Time after Programming
(high voltage discharge time)
Delay to allow Self-Timed Data Write or
Bulk Erase to occur
Data Write Polling Time
Input Data Hold Time from MCLR/V
V
Data Out Valid from SCLK 
PGM Setup Time to MCLR/V
(minimum programming time)
PWRT
DD
is the Instruction Cycle Time, T
Setup Time to MCLR/V
(if enabled) + 1024 T
PP
PP
PP
Rise Time to enter
Characteristic
OSC
PP
PP
(for LP, HS, HS/PLL, and XT modes only)


PWRT
PP
PP

is the Power-up Timer Period, and T
V
0.8 V
DD
2.00
9.00
2.00
4.50
Min
V
100
100
40
40
15
15
40
40
20
10
10
—
—
—
—
—
1
5
4
2
2
SS
– 0.7
DD
0.2 V
13.25
IL
Max
5.50
5.50
5.50
V
300
0.6
1.0
10
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DD
and V
DD
IHH
Units
; this can cause spurious program
mA
A
ms
ms
ms
pF
s
ns
ns
ns
ns
ns
ns
ns
ns
s
s
ns
ns
s
V
V
V
V
V
V
V
V
 2010 Microchip Technology Inc.
Normal programming
Bulk erase operations
I
I
To meet AC specifications
(Note 1)
OSC
OL
OH
= 8.5 mA @ 4.5V
= -3.0 mA @ 4.5V
is the Oscillator Period.
Conditions