PIC18F8720-I/PT Microchip Technology, PIC18F8720-I/PT Datasheet - Page 3

• Manufacturer Part Number: PIC18F8720-I/PT
• Description: IC MCU FLASH 64KX16 EE 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8720-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Eeprom Size: 1K x 8
• Ram Size: 3.75K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.75 KB
• Interface Type: I2C/SPI/USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 68
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183032, DM183022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6. Module: DAW Instruction
EXAMPLE 1:
7. Module: External Memory Interface
© 2005 Microchip Technology Inc.
MOVLW
ADDLW
BTFSC
INCFSZ byte2
DAW
BTFSC
INCFSZ byte2
This is repeated for each DAW instruction
The DAW instruction may improperly clear the
Carry bit (STATUS<0>) when executed.
Work around
Test the Carry bit state before executing the DAW
instruction. If the Carry bit is set, increment the
next higher byte to be added, using an instruction
such as INCFSZ (this instruction does not affect
any Status flags and will not overflow a BCD
nibble). After the DAW instruction has been
executed, process the Carry bit normally (see
Example 1).
Date Codes that pertain to this issue:
All engineering and production devices.
When performing writes on the external memory
interface, a short glitch is present on the LB and
UB lines. The length of the glitch is proportional to
F
temperature. The glitch occurs well before the
WRH line is asserted and no adverse affect on the
operation of the external memory interface has
been observed.
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
OSC
0x80
0x80
STATUS,C
STATUS,C
and also may vary with process, voltage and
(PIC18F8720 and
PIC18F8620 only)
PROCESSING THE CARRY
BIT DURING BCD ADDITIONS
; .80 (BCD)
; .80 (BCD)
; test C
; inc next higher LSB
; test C
; inc next higher LSB
PIC18F6620/8620/6720/8720
8. Module: MSSP (All I
The Buffer Full (BF) flag bit of the SSPSTAT regis-
ter (SSPSTAT<0>) may be inadvertently cleared
even when the SSPBUF register has not been
read. This will occur only when the following two
conditions occur simultaneously:
• The four Least Significant bits of the BSR
• Any instruction that contains C9h in its 8 Least
Work around
All work arounds will involve setting the contents of
BSR<3:0> to some value other than 0Fh.
In addition to those proposed below, other
solutions may exist.
1. When developing or modifying code, keep
2. If accessing a part of Bank 15 is required and
3. If pointing the BSR to Bank 15 is unavoidable,
Date Codes that pertain to this issue:
All engineering and production devices.
register are equal to 0Fh (BSR<3:0> = 1111);
and
Significant bits (i.e., register file addresses,
literal data, address offsets, etc.) is executed.
these guidelines in mind:
• Assign 12-bit addresses to all variables.
• Do not set the BSR to point to Bank 15
• Allow the assembler to manipulate the
the use of Access Banking is not possible,
consider using indirect addressing.
review the absolute file listing. Verify that no
instructions contain C9h in the 8 Least
Significant bits while the BSR points to Bank 15
(BSR = 0Fh).
This allows the assembler to know when
Access Banking can be used.
(BSR = 0Fh).
access bit present in most instructions.
Accessing the SFRs in Bank 15 will be done
through the Access Bank. Continue to use
the BSR to select all GPR Banks.
2
C™ and SPI™ Modes)
DS80129J-page 3