AT32UC3A3256-ALUT Atmel, AT32UC3A3256-ALUT Datasheet - Page 65

• Manufacturer Part Number: AT32UC3A3256-ALUT
• Description: IC MCU AVR32 256KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A3256-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, I2S, JTAG, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AVR UC3
• No. Of I/o's: 110
• Ram Memory Size: 128KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Package: 144LQFP
• Device Core: AVR
• Family Name: AT32
• Maximum Speed: 66 MHz
• Number Of Programmable I/os: 110
• On-chip Adc: 8-chx10-bit
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 10-6. SMC Signals for NRD and NRW Controlled Accesses.
10.10.2
Table 10-35. SDRAM Clock Signal.
Note:
Table 10-36. SDRAM Clock Signal
32072C–AVR32–2010/03
A0/A1/NBS[3:0]
Symbol
1/(t
Symbol
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
CPSDCK
D0 - D15
A2-A25
NWE
NRD
NCS
1. The maximum frequency of the SDRAMC interface is the same as the max frequency for the HSB.
)
1
2
3
4
5
6
7
8
9
10
11
12
SDRAM Signals
Parameter
SDRAM Controller Clock Frequency
Parameter
SDCKE High before SDCK Rising Edge
SDCKE Low after SDCK Rising Edge
SDCKE Low before SDCK Rising Edge
SDCKE High after SDCK Rising Edge
SDCS Low before SDCK Rising Edge
SDCS High after SDCK Rising Edge
RAS Low before SDCK Rising Edge
RAS High after SDCK Rising Edge
SDA10 Change before SDCK Rising Edge
SDA10 Change after SDCK Rising Edge
Address Change before SDCK Rising Edge
Address Change after SDCK Rising Edge
These timings are given for 10 pF load on SDCK and 40 pF on other signals.
SMC9
SMC19
SMC7
SMC20
SMC3
SMC4
SMC5
SMC6
SMC8
SMC45
SMC43
SMC42
SMC37
SMC38
SMC39
SMC40
SMC41
SMC44
Conditions
Conditions
SMC9
SMC1
SMC2
SMC8
SMC7
SMC3
SMC4
SMC5
SMC6
Min.
Min.
7.4
3.2
2.9
7.5
1.6
7.2
2.3
7.6
1.9
6.2
2.2
7
AT32UC3A3/A4
SMC33
1/(t
SMC23
Max.
Max.
cpcpu
(1)
SMC24
SMC32
)
SMC31
SMC25
SMC26
SMC29
SMC30
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
65