LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 61
![IC MCU 32BIT 32KB FLASH 48LQFP](/photos/6/64/66484/568-48-lqfp_sot313-2_sml.jpg)
LPC1313FBD48,151
Manufacturer Part Number
LPC1313FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1313FBD48,151
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
42
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
OM11041
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
LPC1000
Maximum Speed
72 MHz
Number Of Programmable I/os
42
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4914
935289651151
935289651151
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1313FBD48,151
Manufacturer:
MAXIM
Quantity:
1 560
Company:
Part Number:
LPC1313FBD48,151
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
17. Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
7.2
7.3
7.4
7.5
7.6
7.6.1
7.6.2
7.7
7.8
7.8.1
7.9
7.9.1
7.9.1.1
7.10
7.10.1
7.11
7.11.1
7.12
7.12.1
7.13
7.13.1
7.14
7.14.1
7.15
7.16
7.16.1
7.17
7.17.1
7.17.1.1
7.17.1.2
7.17.1.3
7.17.2
7.17.3
7.17.4
LPC1311_13_42_43
Product data sheet
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . 16
On-chip flash program memory . . . . . . . . . . . 16
Nested Vectored Interrupt Controller
(NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Fast general purpose parallel I/O . . . . . . . . . . 18
USB interface (LPC1342/43 only) . . . . . . . . . 19
Full-speed USB device controller . . . . . . . . . . 19
SSP serial I/O controller . . . . . . . . . . . . . . . . . 20
I
General purpose external event
counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 21
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9
Architectural overview . . . . . . . . . . . . . . . . . . 16
ARM Cortex-M3 processor . . . . . . . . . . . . . . . 16
On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 16
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 16
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 18
IOCONFIG block . . . . . . . . . . . . . . . . . . . . . . 18
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
System tick timer . . . . . . . . . . . . . . . . . . . . . . 22
Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 22
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clocking and power control . . . . . . . . . . . . . . 22
Integrated oscillators . . . . . . . . . . . . . . . . . . . 22
Internal RC oscillator . . . . . . . . . . . . . . . . . . . 24
System oscillator . . . . . . . . . . . . . . . . . . . . . . 24
Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 24
System PLL and USB PLL . . . . . . . . . . . . . . . 24
Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Wake-up process . . . . . . . . . . . . . . . . . . . . . . 24
2
C-bus serial I/O controller . . . . . . . . . . . . . . 20
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 10 August 2010
7.17.5
7.17.5.1
7.17.5.2
7.17.5.3
7.18
7.18.1
7.18.2
7.18.3
7.18.4
7.18.5
7.18.6
7.18.7
7.18.8
7.18.9
7.19
8
9
9.1
9.2
9.3
9.4
10
10.1
10.2
10.3
10.4
10.5
10.6
10.7
11
11.1
11.2
11.3
11.4
11.5
11.6
12
13
14
15
15.1
15.2
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 28
Static characteristics . . . . . . . . . . . . . . . . . . . 29
Dynamic characteristics. . . . . . . . . . . . . . . . . 42
Application information . . . . . . . . . . . . . . . . . 50
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 55
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 57
Revision history . . . . . . . . . . . . . . . . . . . . . . . 58
Legal information . . . . . . . . . . . . . . . . . . . . . . 59
Power control . . . . . . . . . . . . . . . . . . . . . . . . . 25
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 25
Deep power-down mode . . . . . . . . . . . . . . . . 25
System control . . . . . . . . . . . . . . . . . . . . . . . . 25
Start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Brownout detection . . . . . . . . . . . . . . . . . . . . 26
Code security
(Code Read Protection - CRP) . . . . . . . . . . . 26
Boot loader. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 27
AHB-Lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
External interrupt inputs . . . . . . . . . . . . . . . . . 27
Memory mapping control . . . . . . . . . . . . . . . . 27
Emulation and debugging . . . . . . . . . . . . . . . 27
BOD static characteristics . . . . . . . . . . . . . . . 34
Power consumption . . . . . . . . . . . . . . . . . . . 34
Peripheral power consumption . . . . . . . . . . . 37
Electrical pin characteristics. . . . . . . . . . . . . . 38
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 42
External clock. . . . . . . . . . . . . . . . . . . . . . . . . 42
Internal oscillators . . . . . . . . . . . . . . . . . . . . . 43
I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
I
SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 46
USB interface
(LPC1342/43 only) . . . . . . . . . . . . . . . . . . . . . 49
Suggested USB interface solutions
(LPC1342/43 only) . . . . . . . . . . . . . . . . . . . . . 50
XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
XTAL Printed-Circuit Board
(PCB) layout guidelines . . . . . . . . . . . . . . . . . 52
Standard I/O pad configuration . . . . . . . . . . . 53
Reset pad configuration . . . . . . . . . . . . . . . . . 54
ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 54
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 59
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2
C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
32-bit ARM Cortex-M3 microcontroller
LPC1311/13/42/43
© NXP B.V. 2010. All rights reserved.
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