LPC1342FHN33,551 NXP Semiconductors, LPC1342FHN33,551 Datasheet - Page 49

• Manufacturer Part Number: LPC1342FHN33,551
• Description: IC MCU 32BIT 16KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1342FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4946; 935289656551

NXP Semiconductors
Table 18.
C
[1]
LPC1311_13_42_43
Product data sheet
Symbol
t
t
t
V
t
t
t
t
t
t
r
f
FRFM
FEOPT
FDEOP
JR1
JR2
EOPR1
EOPR2
Fig 25. Differential data-to-EOP transition skew and EOP width
L
CRS
= 50 pF; R
Characterized but not implemented as production test. Guaranteed by design.
T
differential
data lines
PERIOD
Dynamic characteristics: USB pins (full-speed)
pu
= 1.5 kΩ on D+ to V
10.7 USB interface (LPC1342/43 only)
Parameter
rise time
fall time
differential rise and fall time
matching
output signal crossover voltage
source SE0 interval of EOP
source jitter for differential transition
to SE0 transition
receiver jitter to next transition
receiver jitter for paired transitions
EOP width at receiver
EOP width at receiver
n × T
differential data to
crossover point
DD
SE0/EOP skew
PERIOD
, unless otherwise specified.
All information provided in this document is subject to legal disclaimers.
+ t
FDEOP
Rev. 3 — 10 August 2010
Conditions
10 % to 90 %
10 % to 90 %
see
see
10 % to 90 %
must reject as
EOP; see
Figure 25
must accept as
EOP; see
Figure 25
t
r
/ t
f
Figure 25
Figure 25
crossover point
extended
[1]
[1]
32-bit ARM Cortex-M3 microcontroller
Min
7.7
-
1.3
160
−2
−18.5
−9
40
82
8.5
LPC1311/13/42/43
source EOP width: t
receiver EOP width: t
Typ
-
-
-
-
-
-
-
-
-
-
© NXP B.V. 2010. All rights reserved.
Max
13.8
13.7
109
2.0
175
+5
+18.5
+9
-
-
FEOPT
002aab561
EOPR1
, t
EOPR2
Unit
ns
ns
%
V
ns
ns
ns
ns
ns
ns
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