P87C52SFAA,512 NXP Semiconductors, P87C52SFAA,512 Datasheet - Page 15
![IC 80C51 MCU 8K OTP 44-PLCC](/photos/6/98/69845/568-44-plcc_sot187-2_sml.jpg)
P87C52SFAA,512
Manufacturer Part Number
P87C52SFAA,512
Description
IC 80C51 MCU 8K OTP 44-PLCC
Manufacturer
NXP Semiconductors
Series
87Cr
Datasheet
1.P87C52UBAA512.pdf
(38 pages)
Specifications of P87C52SFAA,512
Core Processor
8051
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, UART/USART
Peripherals
POR
Number Of I /o
32
Program Memory Size
8KB (8K x 8)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Processor Series
P87C5x
Core
80C51
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
568-1249-5
935252890512
P87C52SFAA
935252890512
P87C52SFAA
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
P87C52SFAA,512
Manufacturer:
NXP Semiconductors
Quantity:
10 000
1. Capture/reload occurs only on timer/counter overflow.
2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate
Philips Semiconductors
Table 5. Timer 2 as a Timer
Table 6. Timer 2 as a Counter
NOTES:
Enhanced UART
The UART operates in all of the usual modes that are described in
the first section of Data Handbook IC20, 80C51-Based 8-Bit
Microcontrollers . In addition the UART can perform framing error
detect by looking for missing stop bits, and automatic address
recognition. The UART also fully supports multiprocessor
communication.
When used for framing error detect the UART looks for missing stop
bits in the communication. A missing bit will set the FE bit in the
SCON register. The FE bit shares the SCON.7 bit with SM0 and the
function of SCON.7 is determined by PCON.6 (SMOD0) (see
Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7
functions as SM0 when SMOD0 is cleared. When used as FE
SCON.7 can only be cleared by software. Refer to Figure 8.
Automatic Address Recognition
Automatic Address Recognition is a feature which allows the UART
to recognize certain addresses in the serial bit stream by using
hardware to make the comparisons. This feature saves a great deal
of software overhead by eliminating the need for the software to
examine every serial address which passes by the serial port. This
feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART
modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be
automatically set when the received byte contains either the “Given”
address or the “Broadcast” address. The 9 bit mode requires that
the 9th information bit is a 1 to indicate that the received information
is an address and not data. Automatic address recognition is shown
in Figure 9.
The 8 bit mode is called Mode 1. In this mode the RI flag will be set
if SM2 is enabled and the information received has a valid stop bit
following the 8 address bits and the information is either a Given or
Broadcast address.
Mode 0 is the Shift Register mode and SM2 is ignored.
Using the Automatic Address Recognition feature allows a master to
selectively communicate with one or more slaves by invoking the
Given slave address or addresses. All of the slaves may be
contacted by using the Broadcast address. Two special Function
Registers are used to define the slave’s address, SADDR, and the
address mask, SADEN. SADEN is used to define which bits in the
2000 Aug 07
80C51 8-bit microcontroller family
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
16-bit Auto-Reload
16-bit Capture
Baud rate generator receive and transmit same baud rate
Receive only
Transmit only
16-bit
Auto-Reload
generator mode.
MODE
MODE
MODE
MODE
INTERNAL CONTROL (Note 1)
INTERNAL CONTROL (Note 1)
15
uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and
SADDR are to b used and which bits are “don’t care”. The SADEN
mask can be logically ANDed with the SADDR to create the “Given”
address which the master will use for addressing each of the slaves.
Use of the Given address allows multiple slaves to be recognized
while excluding others. The following examples will help to show the
versatility of this scheme:
Slave 0
Slave 1
In the above example SADDR is the same and the SADEN data is
used to differentiate between the two slaves. Slave 0 requires a 0 in
bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is
ignored. A unique address for Slave 0 would be 1100 0010 since
slave 1 requires a 0 in bit 1. A unique address for slave 1 would be
1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be
selected at the same time by an address which has bit 0 = 0 (for
slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed
with 1100 0000.
In a more complex system the following could be used to select
slaves 1 and 2 while excluding slave 0:
Slave 0
Slave 1
Slave 2
In the above example the differentiation among the 3 slaves is in the
lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be
it can be uniquely addressed by 1110 and 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0
00H
01H
34H
24H
14H
02H
03H
SADDR =
SADEN =
Given
SADDR =
SADEN =
Given
SADDR =
SADEN =
Given
SADDR =
SADEN =
Given
SADDR =
SADEN =
Given
80C51/87C51/80C52/87C52
=
=
=
=
=
T2CON
TMOD
EXTERNAL CONTROL (Note 2)
EXTERNAL CONTROL (Note 2)
1100 0000
1111 1101
1100 00X0
1100 0000
1111 1110
1100 000X
1100 0000
1111 1001
1100 0XX0
1110 0000
1111 1010
1110 0X0X
1110 0000
1111 1100
1110 00XX
0AH
0BH
08H
09H
36H
26H
16H
Product specification